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先看代码：
library ieee;
use ieee.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pll1 is
port (
v1,CP,en,d,c,b,a:in std_logic;
vout:out std_logic
);
end pll1;
architecture pll_arch of pll1 is
signal temp1,temp2: std_logic;--a_bxulie
signal tout1,tout2: std_logic;--a_bxulie
signal v2: std_logic;--v2<=VOUT
signal vd:std_logic;--clk<=CP
signal updn,up,dn:std_logic;--updn<=vd
signal cq,k,m:std_logic_vector(15 downto 0); --开始
signal out1,out2:std_logic;
signal dir:std_logic_vector(3 downto 0); --以上kcount信号
signal inc,dec:std_logic;
signal count : integer range 0 to 63; --开始
signal fin : std_logic;
signal addtemp,dectemp: std_logic;--以上ncount信号
begin
dir<=d&c&b&a;
with dir select
m<="0000000000000111"when"0001",
"0000000000001111"when"0010",
"0000000000011111"when"0011",
"0000000000111111"when"0100",
"0000000001111111"when"0101",
"0000000011111111"when"0110",
"0000000111111111"when"0111",
"0000001111111111"when"1000",
"0000011111111111"when"1001",
"0000111111111111"when"1010",
"0001111111111111"when"1011",
"0011111111111111"when"1100",
"0111111111111111"when"1101",
"1111111111111111"when"1110",
"0000000000000111"when others;
process(v1,v2) --EXOR
begin
VD<=V1 xor V2;
updn<=VD;
end process;
process(CP,en,updn,k,cq) --kcount
begin
if CP'event and CP='1' then
k<=m;
if en='1' then
if updn='0' then
if cq<k then cq<=cq+1;
else cq<=(others=>'0');
end if;
else
if cq>0 then cq<=cq-1;
else cq<=k;
end if;
end if;
else cq<=(others=>'0');
end if;
end if;
end process;
process(en,updn,cq,k)
begin
if en='1' then
if updn='0' then
if cq=k then out1<='1';
else out1<='0';
end if;
out2 <='0';
else
if cq="00000000000000000"then out2<='1';
else out2<='0';
end if;
out1<='0';
end if;
else out1<='0';out2<='0';
end if;
up<=out1;dn<=out2;
end process;
process(cp)--2分频
begin
if cp'event and cp='1' then
temp1<=not temp1;
end if;
end process;
process(cp)--2分频
begin
if cp'event and cp='0' then
temp2<=not temp2;
end if;
end process;
tout2<=temp1 and temp2;
tout1<=(not temp1) and (not temp2);
--clkao<=tout1;
--clkbo<=tout2;
process (tout1)--脉冲加减控制
begin
addtemp<=up and tout1;
end process;
process(tout2)
begin
dectemp<=(not dn) and tout2;
end process;
FIN<=addtemp or dectemp;--是ctrl的fout，ncounter的fin
process (FIN)
begin
if rising_edge(FIN) then
count<=count+1;
if count>=31 then
v2<='1';
else v2<='0';
end if;
end if;
vout<=v2;
end process;
end pll_arch;
再看仿真图
(原文件名:12.jpg) |
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发表于 2010-12-2 17:02:45
楼主
哎