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楼主 |
发表于 2010-11-19 22:42:21
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今天收到ATMEL官方恢复:
DCLK is the divider of master clock. It should be square wave in the master clock range. So below are the suggestions:
1> Please check the input master clock for the LCDC, if it is square wave in different frequency.
2> For SAM9261, 320X240 is the normal size we have tested. I’m afraid that 800X600 maybe too big for SAM9261. Please try to use the smaller size LCD.
有点不爽,资料上说能支持到2040x2048难道是拿来显摆的么?
我不是拿来玩的,是实际的项目,不是说换就换的。。。
幸亏搞定,看来本论坛才是高手云集的地方,有真正实践的经验。 |
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