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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SDRAMINTERFACE is
Port ( clk,exreset :in STD_LOGIC; --------clk是125MSDRAM的反相,这样相当于信号在负沿输出,靠正沿打入SDRAM
clke : out STD_LOGIC;
ncs : out STD_LOGIC;
nwe : out STD_LOGIC;
ncas : out STD_LOGIC;
nras : out STD_LOGIC;
dqml : out STD_LOGIC;
dqmh : out STD_LOGIC;
ba0 : out STD_LOGIC;
ba1 : out STD_LOGIC;
initfinish: out STD_LOGIC;
logicaddr:in STD_LOGIC_VECTOR (23 downto 0);
sdramaddr : out STD_LOGIC_VECTOR (12 downto 0);
sdramdata : inout STD_LOGIC_VECTOR (15 downto 0));
end SDRAMINTERFACE;
architecture Behavioral of SDRAMINTERFACE is
signal reset:STD_LOGIC;
signal resetcount:integer range 0 to 30000;
begin
control:process(reset,clk)
begin
if reset='1' then
clke<='0';
ncs<='1';
ncas<='1';
nras<='1';
nwe<='1';
dqml<='0';
dqmh<='0';
ba0<='0';
ba1<='0';
sdramdata<="ZZZZZZZZZZZZZZZZ";
elsif falling_edge(clk) then
clke<='1';
case resetcount is
when 14502=> --nop
ncs<='0';
when 14510=> --prechange,等待Trp 20ns=3clk
nras<='0';
--ncas<='1';
nwe<='0';
sdramaddr(10)<='1';
when 14513=> --autorefresh
ncas<='0';
nwe<='1';
when 14514=> --nop,66ns,等待自动刷新完成
ncas<='1';
nras<='1';
when 14523=> --先保险起见,多一个时钟,发第二次的自动刷新
nras<='0';
ncas<='0';
when 14524=>
ncas<='1';
nras<='1';
when 14533=> --loadmoderegister
nras<='0';
ncas<='0';
nwe<='0';
sdramaddr<="0000000110111"; --全页突发
when 14534=> --nop,66ns,等待自动刷新完成
nras<='1';
ncas<='1';
nwe<='1';
when others=>
在这里加上SDARM控制代码,暂时略去
end case;
end if;
end process control;
resetcontrol:process(clk,exreset)
begin
if exreset='1' then
initfinish<='1';
reset<='1';
resetcount<=0;
--resetcount<=14495; ------仿真时用
elsif falling_edge(clk) then
if resetcount<14540 then
resetcount<=resetcount+1;
if resetcount>14500 then
reset<='0';
end if;
else
initfinish<='0'; -----到这边时完成了上电初始化工作
end if;
end if;
end process resetcontrol;
end Behavioral; |
阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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