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ISE综合后PALCE&ROUTE
ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <DEBUG_0_OBUF_BUFG> is placed at site <BUFGMUX_X2Y0>. The IO component <AC97Clk>
is placed at site <PAD184>. This will not allow the use of the fast path between the IO and the Clock buffer. If
this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the
.ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is
highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be
corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "AC97Clk" CLOCK_DEDICATED_ROUTE = FALSE; >
但板子做好了,不可能将它引到全局时钟脚上
不知如何在ISE中修改约束文件 |
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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