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《Quartus II 调用Modelsim仿真实例》
编写 modelsim_test.v 文件 Quartus II 编译通过
编写 tb_test.v 文件
打开Modelsim ，New --Library；
Compile 工程文件夹下 3个文件，
tb_test.v
maxii_atoms.v
modelsim_test.vo 通过
然后 双击 vtf_test
即Simulation，出错，出错信息如下
# vsim work_test.vtf_test
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: F:/Project/Modelsim/test1/simulation/modelsim/modelsim_test.vo(46): Unable to access $sdf_annotate file pathname modelsim_test_v.sdo for reading.
# Loading work_test.vtf_test(fast)
# Loading work_test.modelsim_test(fast)
# ** Warning: (vsim-3010) [TSCALE] - Module 'modelsim_test' has a `timescale directive in effect, but previous modules do not.
# Region: /vtf_test/u1
# Loading work_test.maxii_io(fast)
# Loading work_test.maxii_lcell(fast)
# Loading work_test.maxii_asynch_lcell(fast)
# Loading work_test.maxii_lcell_register(fast)
# Loading work_test.maxii_io(fast__1)
# ** Error: (vsim-SDF-3894) modelsim_test_v.sdo: Compiled SDF file was not found.
# ** Error: (vsim-7) Failed to open SDF file "modelsim_test_v.sdo" in read mode.
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "modelsim_test_v.sdo".
# Time: 0 ps Iteration: 0 Region: /vtf_test File: F:/Project/Modelsim/test1/simulation/modelsim/tb_test.v
# Error loading design
说 sdf file not found
请问 这个问题如何解？
软件版本 QuartusII 8.1 Modelsim SE PLUS 6.2b
PS:
//**************以下为modelsim_test.v 文件*******************
module modelsim_test(clk,rst_n,div);
input clk;
input rst_n;
output div;
reg div;
always@(posedge clk or negedge rst_n)
if(!rst_n) div<=1'b0;
else div<=~div;
endmodule
//**************以下为tb_test.v 文件*******************
module vtf_test;
reg clk;
reg rst_n;
wire div;
modelsim_test u1(.clk(clk),.rst_n(rst_n),.div(div));
initial begin
clk=0;
forever
#10 clk=~clk;
end
initial begin
rst_n=0;
#1000 rst_n=1;
#1000;
$stop;
end
endmodule |
阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2010-10-8 20:18:48
