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quartus的fitter竟然是基于VPR的

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发表于 2010-9-29 02:02:18 | 显示全部楼层 |阅读模式
orz

原来MAX II也是Stratix class architecture:
General Options:
    Target device is a Stratix class architecture.
        Target device is a MAX II.
    Design name: 'none'
    Maximum Slack Ratio Allowed for Clock-Path Edges: 0.1
    Maximum Slack Ratio Allowed for Synchronization Edges: 0.1
    Minimum delay chain settings will be assumed for all unknown delay chains
    The circuit will be packed into logic blocks first, then
    The circuit will be placed and routed.
    Maximum placement attempts: 1
    Maximum routing (with placement perturbed) attempts: 3
    VPR will skip this many fit attempts: 0
    SSN Optimization is disabled
    Power-driven compile effort is normal
    Initial random seed: 1
    The pack file will be generated
    Graphics will not be displayed.
    Memory allocator activity will be not be logged.
    VPR memory allocator will not write garbage to allocated buffers.

Clustering Options:
    CBE chain breaking limit (desirable): 21
    CBE chain breaking limit (max): 25
    CBE input limit for Qor (low): 20
    CBE input limit for Qor (mid): 21
    CBE input limit for Qor (high): 25
    Clustering timing gain factor: 1
    Clustering timing exponent: 10
    Clustering gain adjustment for size: -0.005
    Clustering path based edge weight gain factor: 10000
    Intercluster delay (in seconds): 1.25e-009
    Delay assumed for unclustered BLEs (in seconds): 9.375e-010
    Clustering pin sharing gain factor: 1000
    Clustering power criticality factor: 1
    Clustering clock power gain: 0
    Clustering RAM conversion permitted LAB usage fraction: 0.95
    Timing analyze during clustering: Once only
    Constrain critical I/O connections: No
    Try to pack LEs into LABs aggressively: No
    Allow packing of LEs that will require shared ALE inputs: Yes
    Allow experimental sibling gain: Yes
    Allow packing of LEs that will require SLM: Yes
    Allow packing of 6-input LEs with non 6-input LEs that will require SLM: No
    Allow packing using soft logic registers: No
    Pick non-gained blocks by using bucket sorting in greedy clustering: No
    Enforce proximity clustering partitions in clustering: Yes
    Perform power optimizations: No
    Perform clock power optimizations: No
    Anneal clustering: Yes

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