帮忙看看为啥报错

ssaweee

module PLL_t(
clk,rst_n,
led0,
ctl_up,
ctl_down
);

input clk;
input rst_n;
input ctl_up,ctl_down;

output led0;

wire locked;
wire clkc0;//150MHz

pll_t        pll_t_inst (
        .areset ( !rst_n ),
        .inclk0 ( clk ),
        .c0 ( clkc0 ),
        .locked ( locked )
        );

       
reg[25:0] cnt0;
       
reg[25:0] count_st=26'h1000;
        always @(posedge clkc0 or negedge rst_n)
        BEGIN
       
        if(!rst_n) cnt0 = count_st;  //这句报错
        else cnt0 <= cnt0+1'b1;
        assign led0=cnt0[24];
        END
       
always @(posedge ctl_up)        //这句报错
        BEGIN
        count_max<=count_st+26'h1000;
       
       
        END
       
        always @(posedge ctl_down)       
        BEGIN
       
        count_max<=count_st-26'h1000;
       
       
        END
endmodule



报错：
Error (10170): Verilog HDL syntax error at m.v(31) near text "if";  expecting "<=", or "="
Error (10170): Verilog HDL syntax error at m.v(36) near text "always";  expecting ".", or "("

oceanx

always @(posedge clkc0 or negedge rst_n)
BEGIN

if(!rst_n) cnt0 = count_st;  //这句报错
else cnt0 <= cnt0+1'b1;
assign led0=cnt0[24];
END


assign 可以写到always里头？

ssaweee

回复【1楼】oceanx  
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