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module test
(
CLK, RSTn,
Pin_Out
);
input CLK;
input RSTn;
output [3:0]Pin_Out;
/****************************************/
parameter T1MS = 16'd19_999;
/***************************************/
reg [15:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 16'd0;
else if( Count1 == T1MS )
Count1 <= 16'd0;
else if( isCount )
Count1 <= Count1 + 1'b1;
else if( !isCount )
Count1 <= 16'd0;
/****************************************/
reg [9:0]Count_MS;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count_MS <= 10'd0;
else if( Count_MS == rTimes )
Count_MS <= 10'd0;
else if( Count1 == T1MS )
Count_MS <= Count_MS + 1'b1;
/******************************************/
reg [3:0]i;
reg [3:0]rPin_Out;
reg [9:0]rTimes;
reg isCount;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
i <= 4'd0;
rPin_Out <= 4'b1000;
isCount <= 1'b0;
rTimes <= 10'd100;
end
else
case( i )
4'd0, 4'd1, 4'd2, 4'd3:
if( Count_MS >= rTimes ) begin rPin_Out <= { rPin_Out[0], rPin_Out[3:1] }; isCount <= 1'b0; i <= i + 1'b1; end
else begin isCount <= 1'b1; rTimes <= 10'd1000; end
4'd4:
begin i <= 4'd0; end
endcase
/******************************************/
assign Pin_Out = rPin_Out;
/******************************************/
endmodule
/============================================================================/
经过调试，比较稳定了，但是不是最好的~有需要的自己看着办吧！ |
阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2010-8-31 17:50:13
