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又谁能帮我看看这个光电编码模块问题在哪?问什么只知道加计数而不知道减计数?
![](http://cache.amobbs.com/bbs_upload782111/files_32/ourdev_576302.jpg)
(原文件名:GD.jpg)
两个模块的代码分别如下:
library ieee;
use ieee.std_logic_1164.all;
entity deepdirect is
port(
A,B :in std_logic;
direct:out bit
);
end deepdirect;
architecture behav of deepdirect is
begin
process(A,B)
begin
if (A 'event and A ='1') then
--wait for 20 ns;
if (B='1') then
direct<='1';
else
direct<='0';
end if;
end if;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity deepcount is
port(
direct :in bit;
A:in std_logic;
q:out std_logic_vector(31 downto 0)
);
end deepcount;
architecture behave of deepcount is
begin
process(A,direct)
variable cou:std_logic_vector(31 downto 0);
variable sel:std_logic_vector(2 downto 0);
variable zhongduan:std_logic;
variable ql: std_logic_vector(7 downto 0);--计数值或初始值
variable qm: std_logic_vector(7 downto 0);
variable qh: std_logic_vector(7 downto 0);
variable qhh: std_logic_vector(7 downto 0);
begin
if (A 'event and A='1') then
if (direct='1' ) then
if (cou="11111111111111111111111111111111") then
cou:="00000000000000000000000000000000" ;
else
cou:=cou+1;
end if;
q<=cou;
else --上提
if (cou="00000000000000000000000000000000") then
cou:="11111111111111111111111111111111" ;
else
cou:=cou-1;
end if;
q<=cou;
end if;
end if;
end process;
end behave;
当A超前B90°时加计数,当A滞后B90°时,减计数,计数值传到q输出
实际效果只有加,没法减。不知何故。 |
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