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问个语法方面的问题啊!现在我有个数据q1是整型的(0——600),要计算下面几个量:seg1<=q/1100;seg2<=(q1 mod 100)/10;
seg3<=q1 mod 10;
seg1,seg2,seg3都是整型。
但是现在编译报错:在VHDL语法中用“/”需要是除数是底数为2的幂。代码如下:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity disp is
Port ( sysclk : in STD_LOGIC;-------50M板级时钟
seg0 : out STD_LOGIC_VECTOR (6 downto 0);
scan0 : out STD_LOGIC_VECTOR (3 downto 0);
dp0 : out STD_LOGIC);
end disp;
architecture Behavioral of disp is
signal q:std_logic_vector(7 downto 0);
signal q1,seg1,seg2,seg3:integer range 0 to 600;
signal cnt3:integer range 0 to 3;
signal data:integer range 0 to 15;
signal cnt:std_logic_vector(24 downto 0);
signal clk:std_logic;
begin
process(sysclk)-----500赫兹分频
begin
if sysclk'event and sysclk='1' then
if cnt=49999 then clk<=not clk;cnt<=(others=>'0');
else cnt<=cnt+1;
end if;
end if;
end process;
process(q)
begin
q1<=conv_integer(q);
seg1<=(q1/100);
seg2<=((q1 mod 100)/10);
seg3<=(q1 mod 10);
end process;
process(clk)--------------用于扫描地址的计数器
begin
if (clk'event and clk='1') then
cnt3<=cnt3+1;
end if;
end process;
-------------------------数码管地址扫描
process(cnt3)
begin
case cnt3 is
when 0 =>scan0<="0001";data<=seg1;dp0<='0';
when 1 =>scan0<="0010";data<=seg2;dp0<='0';
when 2 =>scan0<="0100";data<=seg3;dp0<='1';
when others=>null;
end case;
end process;
-------------------------七段译码
process(data)
begin
case data is ---.gfedcba
when 0=>seg0<="0111111";
when 1=>seg0<="0000110";
when 2=>seg0<="1011011";
when 3=>seg0<="1001111";
when 4=>seg0<="1100110";
when 5=>seg0<="1101101";
when 6=>seg0<="1111101";
when 7=>seg0<="0000111";
when 8=>seg0<="1111111";
when 9=>seg0<="1101111";
when others=>null;
end case;
end process;
end Behavioral;
请问怎么处理呀?代码中一般用到除法时是怎么解决的?我现在就想到用除法器的IP核这个方法,请问还有更好的方法吗?最好在这个现在代码基础上改 |
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