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发表于 2010-8-14 20:21:55
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这是我做滤波器用的一个测试文件,里面包含文件的读写
`define auto_init
`timescale 1ns/1ns
`define INPUT_FILE "fir_in8.txt"
`define OUTPUT_FILE "fir_out31.txt"
module test_ser_fir ();
parameter NOOFDATA = 40000;
parameter FIR_TAP = 125;
parameter FIR_TAPHALF = 63;
parameter IDATA_WIDTH = 8;
//parameter PDATA_WIDTH = 9;
parameter COEFF_WIDTH = 24;
parameter OUT_WIDTH = 31;
parameter CLK_CYCLE = 20;
parameter CLK_HCYCLE = 10;
reg clk;
reg rst_n;
reg [IDATA_WIDTH-1:0] fir_in;
wire [OUT_WIDTH-1:0] fir_out;
reg [IDATA_WIDTH-1:0] memb [1:NOOFDATA];
reg [OUT_WIDTH-1:0] membyte [0:NOOFDATA-1];
reg write;
/*
integer count_w;
integer regcount;
integer handle;
integer k;
*/
integer handle;
reg [18:0] count_w;
reg [5:0] regcount;
reg [18:0] k;
reg [18:0] k0;
ser_fir dut ( clk,rst_n,fir_in,fir_out );
`ifdef auto_init
initial
begin
$readmemb(`INPUT_FILE,memb);
regcount = 0;
count_w = 0;
handle = 0;
clk = 1'b0;
k =0 ;
k0 = 0;
rst_n = 1'b0;
#(10*CLK_CYCLE + CLK_HCYCLE) rst_n = 1'b1;
end
`endif
always #CLK_HCYCLE clk = ~clk;
always @ ( posedge clk or negedge rst_n )
begin
if ( !rst_n )
regcount <= 6'b0;
else
if ( regcount == 6'd63 )
regcount <= 6'b0;
else
regcount <= regcount + 1'b1;
end
always @ ( posedge clk or negedge rst_n )
begin
if ( !rst_n )
begin
fir_in <= 10'b0;
k <= 19'd1;
end
else
if ( regcount==6'd63 )
begin
k <= k + 1'b1;
fir_in <= memb[k];
end
end
always @ ( posedge clk or negedge rst_n )
begin
if ( !rst_n )
k0 <= 19'b0;
else
if ( regcount==6'b0 )
begin
k0 <= k0 + 1'b1;
membyte[k0] <= fir_out;
end
end
always @ ( posedge clk or negedge rst_n )
begin
if ( !rst_n )
write <= 1'b0;
else
begin
if ( k == NOOFDATA )
write <= 1'b1;
end
end
always @ ( posedge write )
begin
handle = $fopen(`OUTPUT_FILE);
$display("writing results to file...");
for ( count_w=0;count_w<NOOFDATA;count_w=count_w+1 )
begin
$fdisplay(handle,"%d",membyte[count_w]);
$display("%d",membyte[count_w]);
end
$fclose(handle);
end
endmodule |
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