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发表于 2010-8-21 11:43:31
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回复【3楼】honsimark
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看来是我的理解有问题.
流水线排序
module cmp(
input clk,
input rst,
input [7:0] data,
output reg [7:0] data1,
output reg [7:0] data2,
output reg [7:0] data3,
output reg [7:0] data4
);
reg [7:0] temp1,temp2,temp3,temp4;
always @ (posedge clk)
if(!rst)
begin
temp1<=8'd0;
temp2<=8'd0;
temp3<=8'd0;
temp4<=8'd0;
end
else
begin
temp1<=data;
temp2<=temp1;
temp3<=temp2;
temp4<=temp3;
end
reg [7:0] t1,t2,t3,t4;
always @ (posedge clk)
begin
sort(temp1,temp2,t1,t2);
sort(temp3,temp4,t3,t4);
end
reg [7:0] t21,t22,t23,t24;
always @ (posedge clk)
begin
t21<=t1;
sort(t2,t3,t22,t23);
t24<=t4;
end
reg [7:0] t31,t32,t33,t34;
always @ (posedge clk)
begin
sort(t21,t22,t31,t32);
sort(t23,t24,t33,t34);
end
always @ (posedge clk)
begin
data1<=t31;
sort(t32,t33,data2,data3);
data4<=t34;
end
/*********交换位置的任务***************/
task sort;
input [7:0] ix,iy;
output [7:0] ox,oy;
if(ix<iy)
begin
ox<=iy;
oy<=ix;
end
else
begin
ox<=ix;
oy<=iy;
end
endtask
endmodule
组合逻辑排序
module sort4(ra,rb,rc,rd,a,b,c,d);
input [3:0] a,b,c,d;
output [3:0] ra,rb,rc,rd;
reg [3:0] ra,rb,rc,rd;
reg [3:0]va,vb,vc,vd;
always @ (a or b or c or d)
begin
{va,vb,vc,vd}={a,b,c,d};
sort(va,vc);
sort(vb,vd);
sort(va,vb);
sort(vc,vd);
sort(vb,vc);
{ra,rb,rc,rd}={va,vb,vc,vd};
end
task sort;
inout [3:0] x,y;
reg [3:0] temp;
if(x>y)
begin
temp=x;
x=y;
y=temp;
end
else
temp=4'd0;
endtask
endmodule
哪种排序方法更优越?为什么? |
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