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发表于 2010-8-5 16:20:55
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sram is
port(CLK :in std_logic;
RST :in std_logic;
HS :OUT std_logic;
VS :OUT std_logic;
STVL :buffer std_logic;
CKV :out std_logic;
OEV :out std_logic;
VCOM :buffer std_logic;
OEH :out std_logic;
STHL :out std_logic;
CPH1 :buffer std_logic;
CPH2 :buffer std_logic;
CPH3 :buffer std_logic;
model:out std_logic
);
end entity;
architecture dd of sram is
signal counter,column,senddata:std_logic_vector(11 downto 0) ;
begin
process(CLK)
begin
if CLK'event and CLK='1' AND RST='1' then
counter<=counter+1;
if counter>=0 and counter<20 then
OEV<='0';
STHL<='0';
OEH<='1';
STVL<='0';
elsif counter>=1500 then
counter<="000000000000";
end if;
if rst='0' then
OEV<='0';
STHL<='0';
OEH<='1';
STVL<='0';
VCOM<='0';
counter<="000000000000";
end if;
if counter=50 then
column<=column+1;
end if;
if column>234 then
column<=(others=>'0');
end if;
if counter=235 THEN
VCOM<=NOT VCOM;
end if;
if counter=133 and (column>0 and column<=234) then
VS<='1';
elsif counter=133 and column=0 then
VS<='0';
end if;
if counter>=423 and counter<=1424 then
HS<='1';
else
HS<='0';
end if;
if counter>=0 and counter<50 then
OEV<='0';
elsif counter>=50 and counter<185 then
OEV<='1';
elsif counter>=185 and counter<216 then
OEV<='0';
OEH<='0';
elsif counter>=216 or counter<50 then
OEV<='0';
OEH<='1';
end if;
if counter>=423 and counter<429 then
STHL<='1';
elsif counter>429 or counter<423 then
STHL<='0';
end if;
if(counter>=133 and counter<1480)and column=1 then
STVL<='1';
else
STVL<='0';
end if;
if counter>=144 and counter<249 then
CKV<='1';
elsif counter>=249 or counter<144 then
CKV<='0';
end if;
if (counter>=425 and counter<1425)then
CPH1<=NOT CPH1;
end if;
if(counter>=0 and counter<=1500)then
CPH2<='0';
CPH3<='0';
model<='1';
end if;
end if;
end process;
end dd; |
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