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才接触Verilog，找了块人家的液晶转接板自己学习学习，也没钱打板子。
转接板上：
2跟地址线，8根数据线，CS,RD,WE信号与外部接口
LCDClk, Hsync Vsync, DE, R0,R1,R2, G0,G1,G2, B0,B1,驱动液晶，目前发现有问题在研究中……
希望有经验的大侠也一起帮忙指导。
主要是以前软件出身，难以一下转化到硬件语言的设计上来，纯技术交流！
把代码贴出来，一起调试：
module TFTDRV(
input GCLK,
output TFT_CLK,
output TFT_Hsync,
output TFT_Vsync,
output TFT_DE,
output TFT_R0_3,
output TFT_R1_4,
output TFT_R2_5,
output TFT_G0_3,
output TFT_G1_4,
output TFT_G2_5,
output TFT_B0_2_4,
output TFT_B1_3_5,
output [19:0]RAM_A,
inout [7:0]RAM_D1,
inout [7:0]RAM_D2,
output RAM_WE1,
output RAM_WE2,
inout [7:0]EB_D,
input [1:0]EB_A,
input EB_CS,
input EB_WR,
input EB_RD,
output EB_BUSY
);
reg [7:0] reg_tft_rgb = 8'b00000000;
reg[19:0]reg_scan_addr = 20'd0; //TFT LCD Scan Data Address
TFT_CTRL U1(
.INCLK(GCLK),
.LCDCLK(TFT_CLK),
.RGB(reg_tft_rgb),
.Hsync(TFT_Hsync),
.Vsync(TFT_Vsync),
.DE(TFT_DE),
.R0_3(TFT_R0_3),
.R1_4(TFT_R1_4),
.R2_5(TFT_R2_5),
.G0_3(TFT_G0_3),
.G1_4(TFT_G1_4),
.G2_5(TFT_G2_5),
.B0_2_4(TFT_B0_2_4),
.B1_3_5(TFT_B1_3_5)
);
//RAM data inout port control
reg reg_ram_we1 = 1'b1; //RAM Read=1/Write=0 Control Signal
reg [7:0]reg_ram_wdr1 = 8'b00000000; //RAM Write Data Reg
assign RAM_D1 = (reg_ram_we1)?8'bzzzz_zzzz:reg_ram_wdr1;
assign RAM_WE1 = reg_ram_we1;
reg reg_ram_we2 = 1'b1; //RAM Read=1/Write=0 Control Signal
reg [7:0]reg_ram_wdr2 = 8'b00000000; //RAM Write Data Reg
assign RAM_D2 = (reg_ram_we2)?8'bzzzz_zzzz:reg_ram_wdr2;
assign RAM_WE2 = reg_ram_we2;
//reg[19:0]reg_ram_addr = 20'h00000; //RAM Address Line
//assign RAM_A = reg_ram_addr;
reg reg_ram_idx = 1;
assign RAM_A = (reg_ram_idx)?reg_scan_addr:reg_cmd_addr;
//Extern Bus Command addres
reg[19:0]reg_cmd_addr = 20'd0;
reg [9:0]reg_cmd_x = 10'd0;
reg [9:0]reg_cmd_y = 10'd0;
parameter XYHL_STA = 1'b0;
parameter XYHL_END = 1'b1;
reg reg_cmd_xyhl = XYHL_STA; //Extern Bus Write X or Y High Or Low Byte
reg reg_rw_ram_flg = 1'b1; //Read = 1; Write = 0;
reg reg_eb_wr_q1 = 1'b1;
reg reg_eb_wr_q2 = 1'b1;
reg reg_eb_rd_q2 = 1'b1;
reg reg_eb_rd_q1 = 1'b1; //Extern Bus Read Signal
reg [7:0]reg_eb_dat =8'd0;
reg reg_eb_busy = 1'b1; //Extern Bus Command Status
assign EB_D = reg_eb_rd_q2?8'bzzzz_zzzz:reg_eb_dat;
assign EB_BUSY = reg_eb_busy;
parameter EBCMD_X = 2'b01; //X address
parameter EBCMD_Y = 2'b10; //Y address
parameter EBCMD_P = 2'b11; //Page Select
parameter EBCMD_C = 2'b00; //Color data
always @ ( negedge GCLK )
begin
if( TFT_CLK == 1 )
reg_tft_rgb = RAM_D1;
else
reg_tft_rgb = reg_tft_rgb;
/*
//Perp. TFT scan for next GCLK
reg_ram_idx <= 1'b1; //for scan addr;
reg_ram_we1 <= 1'b1;
//Now Read/Write
if( reg_eb_busy )
begin
reg_eb_busy <= 1'b0;
if( reg_rw_ram_flg ) //Read;
reg_eb_dat = RAM_D1;
else
reg_eb_dat = reg_eb_dat;
end
end
*/
end
always @ ( posedge GCLK )
begin
//---------EB BUS Oprating--------------------
reg_eb_wr_q1 <= EB_WR; reg_eb_wr_q2 <= reg_eb_wr_q1;
reg_eb_rd_q1 <= EB_RD; reg_eb_rd_q2 <= reg_eb_rd_q1;
if( !EB_WR & reg_eb_wr_q2 & !EB_CS ) //EB Write
begin
case( EB_A[1:0] )
EBCMD_X:
begin
if( reg_cmd_xyhl==XYHL_STA )
begin
reg_cmd_x[9:8] <= EB_D[1:0];
reg_cmd_xyhl <= XYHL_END;
end
else
begin
reg_cmd_x[7:0] <= EB_D[7:0];
reg_cmd_xyhl <= XYHL_STA;
reg_cmd_addr <= reg_cmd_x+reg_cmd_y*10'd800;
end
end
EBCMD_Y:
begin
if( reg_cmd_xyhl==XYHL_STA )
begin
reg_cmd_y[9:8] <= EB_D[1:0];
reg_cmd_xyhl <= XYHL_END;
end
else
begin
reg_cmd_y[7:0] <= EB_D[7:0];
reg_cmd_xyhl <= XYHL_STA;
reg_cmd_addr <= reg_cmd_x+reg_cmd_y*10'd800;
end
end
EBCMD_C:
begin
reg_ram_wdr1 <= EB_D;
reg_cmd_xyhl <= XYHL_STA;
reg_eb_busy <= 1'b1;
reg_rw_ram_flg <= 1'b0; //write
end
EBCMD_P:
begin
// reg_cmd_x[7:0] <= EB_D[7:0];
// reg_cmd_xyhl <= XYHL_STA;
// reg_next_sm <= 3d'2;
reg_rw_ram_flg <= 1'b1;
// reg_cmd_addr <= reg_cmd_x+reg_cmd_y*10'd800;
reg_eb_busy <= 1'b1;
end
endcase
end
//---------RAM Scan Oprating------------------
if( TFT_CLK == 1 )
begin
//Perp. TFT scan for next GCLK
reg_ram_idx <= 1'b1; //for scan addr;
reg_ram_we1 <= 1'b1;
end
else
begin
if( TFT_DE == 1 )
begin
if( reg_scan_addr < 20'd480000 )
reg_scan_addr <= reg_scan_addr+1'b1;
else
reg_scan_addr <= 0;
end
else
begin
if( reg_scan_addr < 20'd480000 )
reg_scan_addr <= reg_scan_addr;
else
reg_scan_addr <= 0;
end
//--------
if( reg_eb_busy )
begin
reg_eb_busy <= 1'b0;
if( reg_rw_ram_flg ) //Read;
reg_ram_we1 <= 1'b1;
else
reg_ram_we1 <= 1'b0;
reg_ram_idx <= 1'b0;
if( reg_cmd_addr < 20'd479999 )
reg_cmd_addr <= reg_cmd_addr+1'b1;
else
reg_cmd_addr <= 0;
end
end
end
endmodule
module TFT_CTRL(
input INCLK,
input [7:0]RGB,
output LCDCLK,
output Hsync,
output Vsync,
output DE,
output R0_3,
output R1_4,
output R2_5,
output G0_3,
output G1_4,
output G2_5,
output B0_2_4,
output B1_3_5
);
//---------TFT LCD Ctrl-----------
//Ref the NL8060bc31-01 LCD Datasheet
reg thp = 1'b0; //assign to TFT_Hsync
reg tvp = 1'b0; //assign to TFT_Vsync
reg h_de = 1'b0; //Hsync de
reg v_de = 1'b0; //Vsync de
reg [9:0]h_counter = 10'b00_0000_0000; //1024 max
reg [9:0]v_counter = 10'b00_0000_0000; //1024 max
reg reg_tft_clk = 1'b0;
always @( posedge INCLK )
reg_tft_clk <= ~reg_tft_clk; //TFT CLK
assign LCDCLK = reg_tft_clk;
//Hsync & Vsync period counter (th&tv)
always @( posedge LCDCLK )
if( h_counter==10'd1023 )//==th-1
begin
h_counter <= 0;
if( v_counter==10'd624 )//==tv-1
v_counter <= 0;
else
v_counter <= v_counter+1'b1;
end
else
h_counter <= h_counter+1'b1;
//Hsync & Vsync & DE line control
assign Hsync = thp;
assign Vsync = tvp;
assign DE = h_de&v_de;
assign R2_5 = RGB[7];
assign R1_4 = RGB[6];
assign R0_3 = RGB[5];
assign G2_5 = RGB[4];
assign G1_4 = RGB[3];
assign G0_3 = RGB[2];
assign B1_3_5 = RGB[1];
assign B0_2_4 = RGB[0];
always @( posedge LCDCLK )
begin
///////////////////////////////////////////////////////////////////
//
// Hsync Line Control
//
///////////////////////////////////////////////////////////////////
//thp period(72)
if( h_counter<7'd72 )//<thp
thp <= 0;
else
thp <= 1;
//thb period(128) thd period(800)
if( h_counter<8'd200 | h_counter>10'd999) //hc<thp+thb | hc>thp+thb+thd-1
h_de <= 0;
else
h_de <= 1;
///////////////////////////////////////////////////////////////////
//
// Vsync Line Control
//
///////////////////////////////////////////////////////////////////
//tvp period(2)
if( v_counter<3'd2 )//tvp
tvp <= 0;
else
tvp <= 1;
//tvb period(22)/tvd period(600)
if( v_counter<5'd24 | v_counter>10'd623) //vc<tvp+tvb | vc>tvp+tvb+tvd-1
v_de <= 0;
else
v_de <= 1;
end
endmodule |
阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2010-8-3 18:44:49
楼主
