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楼主 |
发表于 2010-7-8 16:30:17
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今天又搞了搞,还是不行。
这是我的Verilog HDL设计源文件
`timescale 1ns/1ns
module adder4 (iclk,rst,oclk); //---------PWM OUTPUT TEST
input iclk;
input rst;
output [5:0]oclk;
reg [15:0]counter;
reg [5:0]off;
reg [15:0]pwmwidth;
reg [15:0]pwmperiod;
reg [2:0]counter1;
reg clk;
always @ (posedge iclk or negedge rst)
begin
if(!rst)
begin
counter<=0;
pwmperiod<=16'b1000000000000000;
end
else
begin
if(counter>=pwmperiod-1)
counter<=0;
else
counter<=counter+1;
end
end
always @ (posedge iclk or negedge rst)
begin
if(!rst)
pwmwidth<=16'b0000000100000000;
else
begin
if(counter>=pwmwidth)
off<=6'b111111;
else
off<=6'b000000;
end
end
assign oclk=off;
endmodule |
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