ERROR:Pack:198 - NCD was not produced. All logic was removed from design

jzd19851102

开发板自带的是verilog程序，我学的是VHDL，写流水灯的程序，遇到问题，
程序和报错信息如下
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led is
    Port ( mclk : in  STD_LOGIC;
           led : out  STD_LOGIC_VECTOR (7 downto 0));
end led;

architecture Behavioral of led is
    signal count:std_logic_vector(24 downto 0);
         signal clock:std_logic;
         signal state:std_logic_vector(3 downto 0);
begin
   
  --分频
        process(mclk)
        begin
          if mclk'event and mclk='1' then
            count<=count+1;
          end if;
        end process;
        --divclk<=count(24);
        clock<=count(24);
       
        --流水灯
        process(clock)
          begin
          if clock'event and clock='1' then
--           with state select
--                  led<=0000_0001 when 0000
--                       0000_0010 when 0001
--                                 0000_0010 when 0010
--                                 0000_0100 when 0100
--                                 0000_1000 when 0101
--                                 0000_1010 when 0110
--                                 0000_0010 when 0111
--                                 0000_0010 when 1000
    case state is
           when "0000" =>led<="00000001";
                when "0001" =>led<="00000010";
           when "0010" =>led<="00000100";
                when "0011" =>led<="00001000";
                when "0100" =>led<="00010000";
                when "0101" =>led<="00100000";
                when "0110" =>led<="10000000";
                when "0111" =>led<="10000000";
                when "1000" =>led<="01000000";
                when "1001" =>led<="00100000";
                when "1010" =>led<="00010000";
                when "1011" =>led<="00001000";
                when "1100" =>led<="00000100";
                when "1101" =>led<="00000010";
                when "1110" =>led<="00000001";
                when "1111" =>led<="11111111";
                when others=> led<="00000000";
                end case;
          end if;
          state<=state+1;
        end process;

end Behavioral;
ERROR:Pack:198 - NCD was not produced. All logic was removed from design.  This
   is usually due to having no input or output PAD connections in the design and
   no nets or symbols marked as 'SAVE'.  You can either add PADs or 'SAVE'
   attributes to the design, or run 'map -u' to disable logic trimming in the
   mapper.

jzd19851102

请高手帮忙指点！
折腾了好久了

steady

同样的错误求助，高手指点指点菜鸟~~~

byeyear

看看有没有选择器件

mailtoyj518168

修改了一下你的程序，编译仿真通过！
附上修改的程序



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity le1 is
    Port ( mclk : in  STD_LOGIC;
           led : out  STD_LOGIC_VECTOR (7 downto 0));
end le1;

architecture Behavioral of le1 is
    signal count:std_logic_vector(24 downto 0);
signal clock:std_logic;
signal state:std_logic_vector(3 downto 0);
begin
   
  --分频
process(mclk)
begin
  if mclk'event and mclk='1' then
    count<=count+1;
  end if;
end process;
--divclk<=count(24);
clock<= count(24); ;

--流水灯
process(clock)
  begin
--  if clock'event and clock='1' then
--    with state select
--   led<=0000_0001 when 0000
--        0000_0010 when 0001
--  0000_0010 when 0010
--  0000_0100 when 0100
--  0000_1000 when 0101
--  0000_1010 when 0110
--  0000_0010 when 0111
--  0000_0010 when 1000
    case state is  
   when "0000" =>led<="00000001";
when "0001" =>led<="00000010";
   when "0010" =>led<="00000100";
when "0011" =>led<="00001000";
when "0100" =>led<="00010000";
when "0101" =>led<="00100000";
when "0110" =>led<="10000000";
when "0111" =>led<="10000000";
when "1000" =>led<="01000000";
when "1001" =>led<="00100000";
when "1010" =>led<="00010000";
when "1011" =>led<="00001000";
when "1100" =>led<="00000100";
when "1101" =>led<="00000010";
when "1110" =>led<="00000001";
when "1111" =>led<="11111111";
when others=> led<="00000000";
end case;
--  end if;
    if clock'event and clock='1' then
                state<=state+1;
        end if ;
end process;

end Behavioral;