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1.我先编写了一个8线/4线优先编码器vhdl代码,编译和仿真都没有问题
2.现在想用两个8线/4线 串成16线/4线优先编码器,我创建了8线/4线编码器的符号ls148,供下面的电路图引用
![](http://cache.amobbs.com/bbs_upload782111/files_29/ourdev_553512.JPG)
(原文件名:16_4优先编码器电路图.JPG)
3.电路编译时,报下面的错误提示:
Info: Elaborating entity "coder164" for the top level hierarchy
Warning: Primitive "NOT" of instance "inst2" not used
Warning: Primitive "NAND2" of instance "inst7" not used
Warning: Primitive "NAND2" of instance "inst8" not used
Warning: Primitive "NAND2" of instance "inst9" not used
Info: Elaborating entity "ls148" for hierarchy "ls148:inst"
Warning (10631): VHDL Process Statement warning at ls148.vhd(14): inferring latch(es) for signal or variable "a", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "a[0]" at ls148.vhd(14)
Info (10041): Inferred latch for "a[1]" at ls148.vhd(14)
Info (10041): Inferred latch for "a[2]" at ls148.vhd(14)
Error: Can't synthesize current design -- Top partition does not contain any logic
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 5 warnings
Error: Peak virtual memory: 182 megabytes
Error: Processing ended: Wed May 12 21:00:08 2010
Error: Elapsed time: 00:00:05
Error: Total CPU time (on all processors): 00:00:05
工程文件:
点击此处下载 ourdev_553513.rar(文件大小:57K) (原文件名:coder164.rar)
谢谢各位~~ |
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