新手请教VHDL问题

jssd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mouse is
        port (Mouse1Xa, Mouse1Xb : in std_logic;
                  ReadIO,WriteIO : inout std_logic;
                  CountOut : out std_logic_vector(7 downto 0));
end mouse;

architecture behave of mouse is
        signal mousedir : std_logic;
        signal counter : std_logic_vector(7 downto 0);
begin

--        ReadIO <= mousedir;      
--        CountOut <= counter;

        process (Mouse1Xa,Mouse1Xb)
        begin
                if(Mouse1Xa'event and Mouse1Xa = '0' and Mouse1Xb = '0') then mousedir <= '0';
                end if;
                if(Mouse1Xb'event and Mouse1Xb = '0' and Mouse1Xa = '0') then mousedir <= '1';
                end if;
        end process;
       
        process (Mouse1Xa)
        begin
                if(Mouse1Xa'event and Mouse1Xa = '1' and mousedir = '0') then
                        counter <= counter + '1';
                end if;
                if(Mouse1Xa'event and Mouse1Xa = '1' and mousedir = '1') then
                        counter <= counter - '1';
                end if;
        end process;
end behave;

为什么加上这两句
        ReadIO <= mousedir;      
        CountOut <= counter;
就出错了呢？
Error (10820): Netlist error at mouse.vhd(21): can't infer register for mousedir because its behavior depends on the edges of multiple distinct clocks
Error (10822): HDL error at mouse.vhd(19): couldn't implement registers for assignments on this clock edge

新手入门。请教各位大虾。。。。谢谢~~~