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Related info:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g/CHDBJIBF.html
The STKALIGN bit reset value in the Configuration and Control Register at address 0xE000ED14 has been inverted. The reset value is now 1, which means that the stack frame is 8-byte aligned by default. Configuration Control Register.
The generic uC/OS-II Cortex M3 port assumes that stack frame is 4-byte aligned, in order to be consistent
with the port you must cleat the reset value to ‘0’
Regards,
Freddy Torres.
Embedded Software Developer.
Micrium.
Email: Freddy.Torres@Micrium.com |
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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