DS18B20 七段数码管显示(Verilog)

tear086 · 发表于 2010-3-12 11:13:58

新近写的，水平有限，欢迎拍砖。

其中DS18B20模块是根据阿虚的VHDL修改而来，在此深表感谢。
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=1079713

(原文件名:图片 001.jpg)

ds18b20_seg7.v
----------------------------------------
module ds18b20_seg7(
  input       CLOCK_50,             // 板载50MHz时钟
  input       Q_KEY,                // 板载按键RST
  //
  inout       DS18B20,
  //
  output [7:0] SEG7_SEG,             // 七段数码管段脚
  output [2:0] SEG7_SEL                // 七段数码管待译位脚
);

//++++++++++++++++++++++++++++++++++++++
// 获取温度值开始
//++++++++++++++++++++++++++++++++++++++
wire [15:0] t_buf;

ds18b20_drive ds18b20_u0(
  .clk(CLOCK_50),
  .rst_n(Q_KEY),
  //
  .one_wire(DS18B20),
  //
  .temperature(t_buf)
);
//-------------------------------------
// 获取温度值结束
//-------------------------------------

//+++++++++++++++++++++++++++++++++++++
// 显示键盘值开始
//+++++++++++++++++++++++++++++++++++++
seg7x8_drive seg7_u0(
  .i_clk          (CLOCK_50),
  .i_rst_n       (Q_KEY),

  .i_turn_off    (8'b1110_1000),          // 熄灭位[2进制]
  .i_dp          (8'b0000_0010),          // 小数点位[2进制]
  // 欲显数据[16进制]
  // 正负位空白十位个位小数位
  .i_data          ({12'h0, t_buf[15:12], 4'h0, t_buf[11:0]}),

  .o_seg          (SEG7_SEG),
  .o_sel          (SEG7_SEL)
);
//-------------------------------------
// 显示键盘值结束
//-------------------------------------

endmodule
----------------------------------------

tear086 · 发表于 2010-3-12 11:14:25

(原文件名:DS18B20 原理图.png)

ds18b20_drive.v
----------------------------------------
module ds18b20_drive(
  input       clk,                   // 50MHz时钟
  input       rst_n,                // 异步复位
  inout       one_wire,             // One-Wire总线
  output [15:0] temperature          // 输出温度值
);

//++++++++++++++++++++++++++++++++++++++
// 分频器50MHz->1MHz 开始
//++++++++++++++++++++++++++++++++++++++
reg [5:0] cnt;                      // 计数子

always @ (posedge clk, negedge rst_n)
  if (!rst_n)
cnt <= 0;
  else
if (cnt == 49)
   cnt <= 0;
else
   cnt <= cnt + 1'b1;

reg clk_1us;                         // 1MHz 时钟

always @ (posedge clk, negedge rst_n)
  if (!rst_n)
clk_1us <= 0;
  else
if (cnt <= 24)                   // 24 = 50/2 - 1
   clk_1us <= 0;
else
   clk_1us <= 1;

//--------------------------------------
// 分频器50MHz->1MHz 结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 延时模块开始
//++++++++++++++++++++++++++++++++++++++
reg [19:0] cnt_1us;                   // 1us延时计数子
reg cnt_1us_clear;                      // 请1us延时计数子

always @ (posedge clk_1us)
  if (cnt_1us_clear)
cnt_1us <= 0;
  else
cnt_1us <= cnt_1us + 1'b1;
//--------------------------------------
// 延时模块结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// DS18B20状态机开始
//++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++++++++++++++++
// 格雷码
parameter S00    = 5'h00;
parameter S0    = 5'h01;
parameter S1    = 5'h03;
parameter S2    = 5'h02;
parameter S3    = 5'h06;
parameter S4    = 5'h07;
parameter S5    = 5'h05;
parameter S6    = 5'h04;
parameter S7    = 5'h0C;
parameter WRITE0  = 5'h0D;
parameter WRITE1  = 5'h0F;
parameter WRITE00 = 5'h0E;
parameter WRITE01 = 5'h0A;
parameter READ0 = 5'h0B;
parameter READ1 = 5'h09;
parameter READ2 = 5'h08;
parameter READ3 = 5'h18;

reg [4:0] state;                      // 状态寄存器
//-------------------------------------

reg one_wire_buf;                   // One-Wire总线缓存寄存器

reg [15:0] temperature_buf;          // 采集到的温度值缓存器（未处理）
reg [5:0] step;                      // 子状态寄存器 0~50
reg [3:0] bit_valid;                // 有效位

always @(posedge clk_1us, negedge rst_n)
begin
  if (!rst_n)
  begin
one_wire_buf <= 1'bZ;
step       <= 0;
state       <= S00;
  end
  else
  begin
case (state)
   S00 : begin
            temperature_buf <= 16'h001F;
            state          <= S0;
         end
   S0 :  begin                      // 初始化
            cnt_1us_clear <= 1;
            one_wire_buf  <= 0;
            state       <= S1;
         end
   S1 :  begin
            cnt_1us_clear <= 0;
            if (cnt_1us == 500)       // 延时500us
            begin
            cnt_1us_clear <= 1;
            one_wire_buf  <= 1'bZ;  // 释放总线
            state       <= S2;
            end
         end
   S2 :  begin
            cnt_1us_clear <= 0;
            if (cnt_1us == 100)       // 等待100us
            begin
            cnt_1us_clear <= 1;
            state       <= S3;
            end
         end
   S3 :  if (~one_wire)             // 若18b20拉低总线,初始化成功
            state <= S4;
         else if (one_wire)       // 否则,初始化不成功,返回S0
            state <= S0;
   S4 :  begin
            cnt_1us_clear <= 0;
            if (cnt_1us == 400)       // 再延时400us
            begin
            cnt_1us_clear <= 1;
            state       <= S5;
            end
         end
   S5 :  begin                      // 写数据
            if    (step == 0)    // 0xCC
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 1)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 2)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 3)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 4)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 5)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 6)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 7)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end

            else if (step == 8)    // 0x44
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 9)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 10)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 11)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 12)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 13)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 14)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;

            end
            else if (step == 15)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end

            // 第一次写完,750ms后,跳回S0
            else if (step == 16)
            begin
            one_wire_buf <= 1'bZ;
            step       <= step + 1'b1;
            state       <= S6;
            end

            // 再次置数0xCC和0xBE
            else if (step == 17)    // 0xCC
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 18)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 19)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 20)
            begin
            step  <= step + 1'b1;
            state <= WRITE01;
            one_wire_buf <= 0;
            end
            else if (step == 21)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 22)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 23)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 24)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end

            else if (step == 25)    // 0xBE
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 26)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 27)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 28)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 29)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 30)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 31)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 32)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end

            // 第二次写完,跳到S7,直接开始读数据
            else if (step == 33)
            begin
            step  <= step + 1'b1;
            state <= S7;
            end
         end
   S6 :  begin
            cnt_1us_clear <= 0;
            if (cnt_1us == 750000 | one_wire)    // 延时750ms!!!!
            begin
            cnt_1us_clear <= 1;
            state       <= S0; // 跳回S0,再次初始化
            end
         end

   S7 :  begin                      // 读数据
            if    (step == 34)
            begin
            bit_valid <= 0;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 35)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 36)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 37)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 38)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 39)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 40)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 41)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 42)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 43)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 44)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 45)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 46)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 47)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 48)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 49)
            begin
            bit_valid <= bit_valid + 1'b1;
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= READ0;
            end
            else if (step == 50)
            begin
            step  <= 0;
            state <= S0;
            end
         end


   //++++++++++++++++++++++++++++++++
   // 写状态机
   //++++++++++++++++++++++++++++++++
   WRITE0 :
         begin
            cnt_1us_clear <= 0;
            one_wire_buf  <= 0;    // 输出0
            if (cnt_1us == 80)       // 延时80us
            begin
            cnt_1us_clear <= 1;
            one_wire_buf  <= 1'bZ;  // 释放总线，自动拉高
            state       <= WRITE00;
            end
         end
   WRITE00 :                      // 空状态
            state <= S5;
   WRITE01 :                      // 空状态
            state <= WRITE1;
   WRITE1 :
         begin
            cnt_1us_clear <= 0;
            one_wire_buf  <= 1'bZ; // 输出1 释放总线，自动拉高
            if (cnt_1us == 80)       // 延时80us
            begin
            cnt_1us_clear <= 1;
            state       <= S5;
            end
         end
   //--------------------------------
   // 写状态机
   //--------------------------------


   //++++++++++++++++++++++++++++++++
   // 读状态机
   //++++++++++++++++++++++++++++++++
   READ0 : state <= READ1;          // 空延时状态
   READ1 :
         begin
            cnt_1us_clear <= 0;
            one_wire_buf  <= 1'bZ; // 释放总线
            if (cnt_1us == 10)       // 再延时10us
            begin
            cnt_1us_clear <= 1;
            state       <= READ2;
            end
         end
   READ2 :                         // 读取数据
         begin
            temperature_buf[bit_valid] <= one_wire;
            state                   <= READ3;
         end
   READ3 :
         begin
            cnt_1us_clear <= 0;
            if (cnt_1us == 55)       // 再延时55us
            begin
            cnt_1us_clear <= 1;
            state       <= S7;
            end
         end
   //--------------------------------
   // 读状态机
   //--------------------------------


   default : state <= S00;
endcase
  end
end

assign one_wire = one_wire_buf;       // 注意双向口的使用
//--------------------------------------
// DS18B20状态机结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 对采集到的温度进行处理开始
//++++++++++++++++++++++++++++++++++++++
wire [15:0] t_buf = temperature_buf & 16'h07FF;

assign temperature[3:0] = (t_buf[3:0] * 10) >> 4;                            // 小数点后一位
assign temperature[7:4] = (t_buf[7:4] >= 10) ? (t_buf[7:4] - 10) : t_buf[7:4];  // 个位
assign temperature[11:8]  = (t_buf[7:4] >= 10) ? (t_buf[11:8] + 1) : t_buf[11:8]; // 十位
assign temperature[15:12] = temperature_buf[12] ? 1 : 0;                         // 正负位，0正1负
//--------------------------------------
// 对采集到的温度进行处理结束
//--------------------------------------

endmodule
----------------------------------------

tear086 · 发表于 2010-3-12 11:14:42

(原文件名:SEG7 原理图.png)

seg7x8_drive.v
----------------------------------------
module seg7x8_drive(
  input       i_clk,
  input       i_rst_n,

  input  [7:0]  i_turn_off,          // 熄灭位[2进制
  input  [7:0]  i_dp,                // 小数点位[2进制
  input  [31:0] i_data,                // 欲显数据[16进制

  output [7:0]  o_seg,                // 段脚
  output [2:0]  o_sel                // 使用74HC138译出位脚
);

//++++++++++++++++++++++++++++++++++++++
// 分频部分开始
//++++++++++++++++++++++++++++++++++++++
reg [16:0] cnt;                      // 计数子

always @ (posedge i_clk, negedge i_rst_n)
  if (!i_rst_n)
cnt <= 0;
  else
cnt <= cnt + 1'b1;

wire seg7_clk = cnt[16];             // (2^17/50M = 2.6114)ms
//--------------------------------------
// 分频部分结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 动态扫描, 生成seg7_addr 开始
//++++++++++++++++++++++++++++++++++++++
reg [2:0]  seg7_addr;                // 第几个seg7

always @ (posedge seg7_clk, negedge i_rst_n)
  if (!i_rst_n)
seg7_addr <= 0;
  else
seg7_addr <= seg7_addr + 1'b1;
//--------------------------------------
// 动态扫描, 生成seg7_addr 结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 译出位码开始
//++++++++++++++++++++++++++++++++++++++
reg [2:0] o_sel_r;                   // 位选码寄存器

// 开发板上SEG7的方向是低位在左，高位在右
// 但是实际上我们看数的方向是高位在左，低位在右
// 故此处将第0位对应DIG[7]，第7位对应DIG[0]
always
  case (seg7_addr)
0 : o_sel_r = 3'b111;             // SEG7[7]
1 : o_sel_r = 3'b110;             // SEG7[6]
2 : o_sel_r = 3'b101;             // SEG7[5]
3 : o_sel_r = 3'b100;             // SEG7[4]
4 : o_sel_r = 3'b011;             // SEG7[3]
5 : o_sel_r = 3'b010;             // SEG7[2]
6 : o_sel_r = 3'b001;             // SEG7[1]
7 : o_sel_r = 3'b000;             // SEG7[0]
  endcase
//--------------------------------------
// 根据seg7_addr, 译出位码结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 选择熄灭码开始
//++++++++++++++++++++++++++++++++++++++
reg turn_off_r;                      // 熄灭码

always
  case (seg7_addr)
0 : turn_off_r = i_turn_off[0];
1 : turn_off_r = i_turn_off[1];
2 : turn_off_r = i_turn_off[2];
3 : turn_off_r = i_turn_off[3];
4 : turn_off_r = i_turn_off[4];
5 : turn_off_r = i_turn_off[5];
6 : turn_off_r = i_turn_off[6];
7 : turn_off_r = i_turn_off[7];
  endcase
//--------------------------------------
// 根据seg7_addr, 选择熄灭码结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 选择小数点码开始
//++++++++++++++++++++++++++++++++++++++
reg dp_r;                            // 小数点码

always
  case (seg7_addr)
0 : dp_r = i_dp[0];
1 : dp_r = i_dp[1];
2 : dp_r = i_dp[2];
3 : dp_r = i_dp[3];
4 : dp_r = i_dp[4];
5 : dp_r = i_dp[5];
6 : dp_r = i_dp[6];
7 : dp_r = i_dp[7];
  endcase
//--------------------------------------
// 根据seg7_addr, 选择小数点码结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 根据seg7_addr, 选择待译段码开始
//++++++++++++++++++++++++++++++++++++++
reg [3:0] seg_data_r;                // 待译段码

always
  case (seg7_addr)
0 : seg_data_r = i_data[3:0];
1 : seg_data_r = i_data[7:4];
2 : seg_data_r = i_data[11:8];
3 : seg_data_r = i_data[15:12];
4 : seg_data_r = i_data[19:16];
5 : seg_data_r = i_data[23:20];
6 : seg_data_r = i_data[27:24];
7 : seg_data_r = i_data[31:28];
  endcase
//--------------------------------------
// 根据seg7_addr, 选择待译段码结束
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
// 根据熄灭码/小数点码/待译段码
// 译出段码，开始
//++++++++++++++++++++++++++++++++++++++
reg [7:0] o_seg_r;                   // 段码寄存器

/*
*    0
*  -------
*  |    |
* 5|  6  |1
*  -------
*  |    |
* 4|    |2
*  ------- . 7
* 3
*/

// 共阳
always @ (posedge i_clk, negedge i_rst_n)
  if (!i_rst_n)
o_seg_r <= 8'hFF;                // 送熄灭码
  else
if(turn_off_r)                   // 送熄灭码
   o_seg_r <= 8'hFF;
else
   if(!dp_r)
      case(seg_data_r)             // 无小数点
      4'h0 : o_seg_r <= 8'hC0;
      4'h1 : o_seg_r <= 8'hF9;
      4'h2 : o_seg_r <= 8'hA4;
      4'h3 : o_seg_r <= 8'hB0;
      4'h4 : o_seg_r <= 8'h99;
      4'h5 : o_seg_r <= 8'h92;
      4'h6 : o_seg_r <= 8'h82;
      4'h7 : o_seg_r <= 8'hF8;
      4'h8 : o_seg_r <= 8'h80;
      4'h9 : o_seg_r <= 8'h90;
      4'hA : o_seg_r <= 8'h88;
      4'hB : o_seg_r <= 8'h83;
      4'hC : o_seg_r <= 8'hC6;
      4'hD : o_seg_r <= 8'hA1;
      4'hE : o_seg_r <= 8'h86;
      4'hF : o_seg_r <= 8'h8E;
      endcase
   else
      case(seg_data_r)             // 加小数点
      4'h0 : o_seg_r <= 8'hC0 ^ 8'h80;
      4'h1 : o_seg_r <= 8'hF9 ^ 8'h80;
      4'h2 : o_seg_r <= 8'hA4 ^ 8'h80;
      4'h3 : o_seg_r <= 8'hB0 ^ 8'h80;
      4'h4 : o_seg_r <= 8'h99 ^ 8'h80;
      4'h5 : o_seg_r <= 8'h92 ^ 8'h80;
      4'h6 : o_seg_r <= 8'h82 ^ 8'h80;
      4'h7 : o_seg_r <= 8'hF8 ^ 8'h80;
      4'h8 : o_seg_r <= 8'h80 ^ 8'h80;
      4'h9 : o_seg_r <= 8'h90 ^ 8'h80;
      4'hA : o_seg_r <= 8'h88 ^ 8'h80;
      4'hB : o_seg_r <= 8'h83 ^ 8'h80;
      4'hC : o_seg_r <= 8'hC6 ^ 8'h80;
      4'hD : o_seg_r <= 8'hA1 ^ 8'h80;
      4'hE : o_seg_r <= 8'h86 ^ 8'h80;
      4'hF : o_seg_r <= 8'h8E ^ 8'h80;
      endcase
//--------------------------------------
// 根据熄灭码/小数点码/待译段码
// 译出段码，结束
//--------------------------------------

assign o_sel = o_sel_r;                // 寄存器输出位选码
assign o_seg = o_seg_r;                // 寄存器输出段码

endmodule
----------------------------------------

AlongChare · 发表于 2010-3-12 12:01:08

MARK

avrwoo · 发表于 2010-3-12 15:25:15

mark

luojiyin · 发表于 2010-3-16 14:37:57

mark

lisn · 发表于 2010-4-12 14:34:36

不错太有才了

DanielDeng · 发表于 2010-4-14 12:57:23

Mark.

sky_walker · 发表于 2010-4-15 11:12:44

Mark.

nishijin · 发表于 2010-4-15 21:46:24

回复【楼主位】tear086 .COM 缺氧
--------------------------------------------------------------------好啊，我正要这个

anxiangbo · 发表于 2010-5-12 15:07:46

记号

xiaobudian · 发表于 2010-5-12 20:27:04

嘿嘿，支持下(～ o ～)~zZ

racemaker · 发表于 2010-5-13 15:08:41

mark!

sunjie718 · 发表于 2010-5-14 23:31:44

cool

zzzvsbbb · 发表于 2010-5-21 15:21:52

回复【楼主位】tear086 .COM 缺氧
-----------------------------------------------------------------------

关于// 对采集到的温度进行处理开始
//++++++++++++++++++++++++++++++++++++++
wire [15:0] t_buf = temperature_buf & 16'h07FF;

assign temperature[3:0] = (t_buf[3:0] * 10) >> 4;                            // 小数点后一位
assign temperature[7:4] = (t_buf[7:4] >= 10) ? (t_buf[7:4] - 10) : t_buf[7:4];  // 个位
assign temperature[11:8]  = (t_buf[7:4] >= 10) ? (t_buf[11:8] + 1) : t_buf[11:8]; // 十位
assign temperature[15:12] = temperature_buf[12] ? 1 : 0;                         // 正负位，0正1负
//--------------------------------------
// 对采集到的温度进行处理结束
//--------------------------------------
我算了一下怎么不对，是否我计算有问题，或理解错误，请指点一下。

luy3728000 · 发表于 2010-5-24 00:17:29

牛。。！菜鸟我正在学习

tear086 · 发表于 2010-5-24 08:41:50

回复【15楼】zzzvsbbb
-----------------------------------------------------------------------

有可能是我的錯誤，請幫忙指出。

jianchangd · 发表于 2010-5-25 23:27:34

谢谢楼主,这真是好东西呀,我初学verilog,最近想实现一个用cpld来测两个触发点的时间(精确到1us)的东西,并用数码管来显示所测时间值.同时还需要做两路PWM模拟DA,请问楼主有这方面的资料或例程吗?能不能共享一下?谢谢!

guo69 · 发表于 2010-5-26 08:35:38

好东西，mark

fly_jony · 发表于 2010-6-26 13:50:43

好佩服楼主，我最近也刚开始学习verilog,向楼主多多学习！

amoFUCK · 发表于 2010-6-26 15:42:04

顶...

lsea · 发表于 2010-6-27 11:53:04

艾米电子我用了一块你的电路板。ec2c8 看你的光盘上的程序有一个测试sram的有点误导啊。

tear086 · 发表于 2010-6-27 12:37:00

感謝樓上哥對我們艾米電子的支持，請您見諒。先前的sram測試例程是亮哥做的，使用SignalTap來查看是否讀寫正確。使用起來沒有任何問題，就是略微麻煩。

oceanx · 发表于 2010-6-28 15:06:53

Mark

zdbinger · 发表于 2010-10-2 15:19:31

非常感谢楼主！我学verilog就是找不到这样完整的例程！

不过还有个地方看不懂：
//+++++++++++++++++++++++++++++++++++++
// 显示键盘值开始
//+++++++++++++++++++++++++++++++++++++
seg7x8_drive seg7_u0(
  .i_clk          (CLOCK_50),
  .i_rst_n       (Q_KEY),

  .i_turn_off    (8'b1110_1000),          // 熄灭位[2进制]
  .i_dp          (8'b0000_0010),          // 小数点位[2进制]
  // 欲显数据[16进制]
  // 正负位空白十位个位小数位
  .i_data          ({12'h0, t_buf[15:12], 4'h0, t_buf[11:0]}),

  .o_seg          (SEG7_SEG),
  .o_sel          (SEG7_SEL)
);
.i_clk          (CLOCK_50),  这行是什么意思呀？

weixintec · 发表于 2010-10-2 17:58:45

good

lostmj · 发表于 2010-10-2 19:34:27

MARK

yuphone · 发表于 2010-10-2 21:14:11

回复【25楼】zdbinger
.i_clk (CLOCK_50), 这行是什么意思呀？
-----------------------------------------------------------------------

例化时钟

kunpeng032 · 发表于 2010-10-3 09:16:40

mark

zdbinger · 发表于 2010-10-3 10:01:11

谢谢艾米电子！明白了！
再次请教一个问题：
always @(posedge i_clk)
      begin
         if(buffer==16'd60000)  //如果这里改成if(buffer>=16'd60000)  就会使宏占用的多16个，是为什么呀？
            begin
            if(flag<7) flag=flag+1'b1;
            else       flag=1'b0;
            buffer=1'b0;
            end
         else
            buffer=buffer+1'b1;
      end

wanwzy · 发表于 2010-10-4 11:22:31

mark

zgxbcf · 发表于 2011-4-8 21:03:34

回复【楼主位】tear086 .COM 缺氧
-----------------------------------------------------------------------

S5 :  begin                      // 写数据
            if    (step == 0)    // 0xCC
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 1)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 2)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 3)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 4)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 5)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 6)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 7)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end

            else if (step == 8)    // 0x44
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 9)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 10)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;
            end
            else if (step == 11)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 12)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 13)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
            else if (step == 14)
            begin
            one_wire_buf <= 0;
            step       <= step + 1'b1;
            state       <= WRITE01;

            end
            else if (step == 15)
            begin
            step  <= step + 1'b1;
            state <= WRITE0;
            end
这里怎么样看出0XCC的呀？

xzf962 · 发表于 2011-4-10 13:56:19

MARK

whf715 · 发表于 2011-12-1 10:28:52

关于// 对采集到的温度进行处理开始
//++++++++++++++++++++++++++++++++++++++
wire [15:0] t_buf = temperature_buf & 16'h07FF;

assign temperature[3:0] = (t_buf[3:0] * 10) >> 4;                            // 小数点后一位
assign temperature[7:4] = (t_buf[7:4] >= 10) ? (t_buf[7:4] - 10) : t_buf[7:4];  // 个位
assign temperature[11:8]  = (t_buf[7:4] >= 10) ? (t_buf[11:8] + 1) : t_buf[11:8]; // 十位
assign temperature[15:12] = temperature_buf[12] ? 1 : 0;                         // 正负位，0正1负
//--------------------------------------
// 对采集到的温度进行处理结束

能不能指点一下这几句是什么意思？

liaopinjia · 发表于 2011-12-8 13:41:47

mark

89712568 · 发表于 2011-12-18 22:26:45

太高深了。。

newselect · 发表于 2011-12-23 08:55:27

感觉臃肿

tongluren · 发表于 2011-12-23 16:44:44

特长了，没安下心来看，总之先mark，以后有时间在看吧~~~

shiqj · 发表于 2011-12-23 17:40:24

mark

robby218 · 发表于 2013-5-9 13:29:08

很好，很清楚，有受益，谢谢。

jlian168 · 发表于 2013-5-9 14:22:24

mark,thanks.

dongwei123 · 发表于 2013-5-10 20:55:48

感谢楼主分享~学习了。

senzi01 · 发表于 2013-6-1 20:23:54

采集出来的温度处理好像有点问题。

//++++++++++++++++++++++++++++++++++++++
// 对采集到的温度进行处理开始
//++++++++++++++++++++++++++++++++++++++
wire [15:0] t_buf = temperature_buf & 16'h07FF;

assign temperature[3:0] = (t_buf[3:0] * 10) >> 4;                            // 小数点后一位
assign temperature[7:4] = (t_buf[7:4] >= 10) ? (t_buf[7:4] - 10) : t_buf[7:4];  // 个位
assign temperature[11:8]  = (t_buf[7:4] >= 10) ? (t_buf[11:8] + 1) : t_buf[11:8]; // 十位
assign temperature[15:12] = temperature_buf[12] ? 1 : 0;                         // 正负位，0正1负
//--------------------------------------
// 对采集到的温度进行处理结束
//--------------------------------------

但是我不知道怎么改..

scutfanyu · 发表于 2013-9-5 18:04:22

haorenyishengpingan

DS18B20 七段数码管显示(Verilog)

阿莫论坛20周年了！感谢大家的支持与爱护！！