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各位大师们,俺们刚开始入手Quartus II,发现无论哪方面都胜过MAX PLUS II(俺原来用的是这个,别笑俺老土),我用的是画图的方法设计的,自己瞎搞点东西就不多提了,就是原理图设计完了后编译没有error,但是有warning,我没有理会,后面就开始分配引脚,很简单的一个异或门,两个输入一个输出,我选型用的是EPM240这颗,2脚输入3脚输出4脚输入,其他没动,然后保存文档,在回到原理图界面就编译不过了,错误提示如下
Error (10500): VHDL syntax error at TEST0.vhd(25) near text "OUT"; expecting an identifier ("out" is a reserved
keyword) ,or "constant", or "file", or "signal", or "variable"
Error (10523): Ignored construct TEST0 at TEST0.vhd(20) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 167 megabytes
Error: Processing ended: Wed Mar 03 11:01:18 2010
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings
Error: Total CPU time (on all processors): 00:00:02
感谢 ourdev 和网友们,问题也许比较RZ~ |
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
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