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自己编的verilog JM12864F代码
之前找了好久，都是VHDL的，自己用verilog写一个，已测试好使，写的不好，见笑！
module lcd12864s(clk,en,rw,rs,data,reset,psb,key1,key2);
input clk;
input reset;
input key1;
input key2;
output [7:0]data;
output rw;
output rs;
output en;
output psb;
reg [7:0]data;
reg [7:0]data1;
reg [50:0]clk_reg;
reg fclk;
reg fclk_reg;
reg [30:0]sum;
reg [30:0]sum1;
reg flag;
reg [7:0]state;
reg [6:0]counter;
reg [6:0]counter1;
reg rw;
reg rs;
wire [6:0]counter2;
always @(posedge clk)
if(!reset)
clk_reg<=0;
else
if(clk_reg<500000)
clk_reg<=clk_reg+1;
else
begin
clk_reg<=0;
fclk<=~fclk;
end
always @(posedge fclk or negedge reset)
begin
if(!reset)
begin
state<=8'h00;
flag<=0;
counter<=0;
counter1<=0;
sum<=0;
sum1<=0;
end
else
begin
case(state)
8'h00:
begin
if(!flag)
begin
flag<=1;
///counter<=0;
sum<=0;
state<=8'h01;
end
else
state<=8'h00;
/* if(sum<'d9999)
begin
sum<=sum+1;
state<=8'h00;
end
else
begin
sum<=0;
state<=8'h00;
end */
end
8'h01:
begin
rs<=0;
rw<=0;
data<=8'h30;
state<=8'h02;
end
8'h02:
begin
rs<=0;
rw<=0;
data<=8'h30;
state<=8'h03;
end
8'h03:
begin
rs<=0;
rw<=0;
data<=8'h0c;
state<=8'h04;
end
8'h04:
begin
rs<=0;
rw<=0;
data<=8'h01;
state<=8'h05;
end
8'h05:
begin
rs<=0;
rw<=0;
data<=8'h06;
state<=8'h07;
end
8'h06:
begin
rs<=0;
rw<=0;
state<=8'h07;
if(counter==7)
begin
counter<=counter+1;
data<=8'h90;
end
else
if(counter==15)
begin
counter<=counter+1;
data<=8'h88;
end
else
if(counter==23)
begin
counter<=counter+1;
data<=8'h98;
end
end
8'h07:
begin
rs<=1;
rw<=0;
// counter1<=counter1+1;
data<=data1;
counter1<=counter1+1;
// data<=8'hC0;
state<=8'h08;
end
8'h08:
begin
rs<=1;
rw<=0;
//data<="吕";
//data<=8'hC0+counter;
// counter1<=counter1+1;
data<=data1;
counter1<=counter1+1;
if(counter<7)
begin
counter<=counter+1;
state<=8'h07;
end
else
if(counter==7)
begin
state<=8'h06;
end
else
if(counter<15)
begin
state<=8'h07;
counter<=counter+1;
end
else
if(counter==15)
begin
state<=8'h06;
end
else
if(counter<23)
begin
state<=8'h07;
counter<=counter+1;
end
else
if(counter==23)
begin
state<=8'h06;
end
else
if(counter<31)
begin
state<=8'h07;
counter<=counter+1;
end
else
state<=8'h09;
end
/* 8'h09: begin
rs<=0;
rw<=1;
if(sum1<'d9999)
begin
sum1<=sum1+1;
state<=8'h09;
end
else
begin
sum1<=0;
state<=8'h09;
end
end
*/
8'h09: begin
rs<=0;
rw<=1;
if(key1==0)
begin
rs<=0;
rw<=0;
data<=8'h02;
counter<=0;
counter1<=0;
// counter1<=(counter1-64)>=0?(counter-64):0;
state<=8'h07;
end
else
if(key2==0)
begin
rs<=0;
rw<=0;
data<=8'h02;
counter<=0;
counter1<='d64;
state<=8'h07;
end
else
if(sum1<'d9999)
begin
sum1<=sum1+1;
state<=8'h09;
end
else
begin
sum1<=0;
state<=8'h09;
end
end
default: state<=8'h00;
endcase
end
end
assign en=fclk;
assign psb=1;
assign counter2=counter1;
abcd aaa(.da(data1),.ddr(counter2));
endmodule
quartus ii 6.0版本ourdev_525867.rar(文件大小:543K) (原文件名:lcd12864s.rar) |
阿莫论坛20周年了！感谢大家的支持与爱护！！
曾经有一段真挚的爱情摆在我的面前，我没有珍惜，现在想起来，还好我没有珍惜……
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发表于 2010-1-14 10:10:03
