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module dec_seg(F,Rt,clk,sem_seg);
input clk,F,Rt;
output sem_seg;
reg [3:0] sem_seg;
//wire [3:0] sem_seg;
wire [3:0] f11out,f22out,f33out,f44out;
reg f11_out,f22_out,f33_out,f44_out;
reg [3:0] choo;
integer m;
//wire [3:0] choos;
count1 top(.Fx(F),.Rst(Rt),.fx1_out(f11out),.fx2_out(f22out),.fx3_out(f33out),.fx4_out(f44out));
assign f11out = f11_out;
assign f22out = f22_out;
assign f33out = f33_out;
assign f44out = f44_out;
always @(posedge clk)
if(m<3)
m=m+1;
else
m=0;
always @(m)
begin
case(m) ---------line 29
0: choo = f11_out;
1: choo = f22_out;
2: choo = f33_out;
3: choo = f44_out;
endcase
end
always @(choo or negedge clk) -------------line 38
begin
case(choo)
4'h0: sem_seg = 8'hc0; // "0"
4'h1 : sem_seg = 8'hf9; // "1"
4'h2 : sem_seg = 8'ha4; // "2"
4'h3 : sem_seg = 8'hb0; // "3"
4'h4 : sem_seg = 8'h99; // "4"
4'h5 : sem_seg = 8'h92; // "5"
4'h6 : sem_seg = 8'h82; // "6"
4'h7 : sem_seg = 8'hf8; // "7"
4'h8 : sem_seg = 8'h80; // "8"
4'h9 : sem_seg = 8'h90; // "9"
endcase
end
endmodule
编译提示:
Analyzing top module <dec_seg>.
WARNING:Xst:905 - "dec_seg.v" line 29: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<f11_out>, <f22_out>, <f33_out>, <f44_out>
ERROR:Xst:902 - "dec_seg.v" line 38: Unexpected event in always block sensitivity list. |
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