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发表于 2010-9-27 01:05:38
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今天的讨论中我突然想到了一种更诡异的配置cy7c68013a的方法，以避开VR 0xa0。
基本不需要FPGA的配合了，也不需要外部RAM，而且可以用更常用的100脚封装！！
首先我们看TRM中的如下内容：
7.4 CPU Reset Effects
The USB host may reset the CPU at any time by downloading the value 0x01 to the CPUCS register.
The basic USB device configuration remains intact through a CPU reset.
Endpoints keep their configuration, the USB Function Address remains the same, and the IO ports retain their
configurations and values. Stalled endpoints remain stalled, data toggles do not change, and the RENUM bit is
unaffected. The only effects of a CPU reset are as follows:
■ USB (INT2) interrupts are disabled, but pending interrupt requests remain pending.
■ When the CPU comes out of reset, pending interrupts are kept pending, but disabled. This gives the firmware writer the
choice of acting on pre-reset USB events, or ignoring them by clearing the pending interrupts before enabling INT2.
■ The breakpoint condition (<font color="red">BREAKPT.3) is cleared.</font>
■ While the CPU is in reset, the EZ-USB enters the Suspend state automatically if a ‘suspend’ condition is detected on the bus.
注意上面的彩色部分，注意是只清除BREAKPT寄存器的第三位。
下面看BREAKPT寄存器的描述：
Bit 3: Break Enable Breakpoint.
The BREAK bit is set when the CPU address bus matches the address held in the bit breakpoint
address registers (0xE606/07). The BKPT pin reflects the state of this bit. Write a '1' to the BREAK bit
to clear it. It is not necessary to clear the BREAK bit if the pulse mode bit (BPPULSE) is set.
Bit 2: BPPULSE Breakpoint Pulse Mode.
Set this bit to ’1’ to pulse the BREAK bit (and BKPT pin) high for eight CLKOUT cycles when the 8051
address bus matches the address held in the breakpoint address registers. When this bit is set to ’0’,
the BREAK bit (and BKPT pin) remains high until it is cleared by firmware.
Bit 1: BPEN Breakpoint Enable.
If this bit is ’1’, a BREAK signal is generated whenever the 16 bit address lines match the value in the
Breakpoint Address registers (BPADDRH:L). The behavior of the BREAK bit and associated BKP pin
signal is either latched or pulsed, depending on the state of the BPPULSE bit.
看出来了么，USB Host的CPU Reset只清除的位其实无关紧要，设想我们的固件上来将BPADDRH:L设置为0x0000，BPEN设为1，
BPPULSE设为0，然后很阴险的将BKPT管脚反向之后接到RESET#管脚(当然常规的电阻电容电路也是要有的)。
那么，一旦上位机重新下载了68013A的程序，那么必然Reset 68013A，那么在68013A从0x0000开始执行程序的时候，立即
会导致BKPT输出1，从而立即把自己重启，重启后，会自动从EEPROM中读取程序，这样我们就有接管了68013A。
只所以设置BPPULSE为0，是因为：
The RESET# pin can also be asserted at any time after the EZ-USB is running. If the EZ-USB’s XTALIN pin is
driven by an external clock source that continues to run while the chip is in reset, RESET# need only be
asserted for 200 μs. Otherwise, it must be asserted for at least 5 ms.
8个CLKOUT周期无论如何不够5ms.
现在，至少从数据手册上看，我的方法是可行的，唯一的疑问是：
(1) CPU Reset是否真的只如数据手册说的，清除BREAK位而不是整个寄存器都清零(只清除一位显然很费劲，这个只清除
一位的功能如果没有测试到，还是有可能被错误实现为清除整个寄存器的)。
(2) 如果在清除BREAK位的时候CPU的地址总线已经是0了，也就是这个0没有被检测到怎么办？
这个是有解决方法的，只要把BPADDRH:L设置为0x0001即可。因为8051所有的跳转指令都不会少于2个字节，所以这个位置
是一定会执行到的。
我们以后当然可以让FPGA来感受BKPT然后控制RESET#，肯定比我上面说的直接反向的办法更灵活(实际上，由于我们的EEPROM
固件无法从68013a那里判断到底是如何启动的它[是刚上电还是USB Host导致的重启]，还是得通过FPGA来保存这个状态信息)。
我马上弄个测试程序，给无机酸，估计今天就能得到结果。
如果证实可行，那我们以前苦恼了那么长时间的问题就解决了，而且68013A方案也真正可行了(前面用EA的方式控制68013A
太浪费FPGA IO了，我们右侧IO非常紧缺)。 |
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楼主: multijtager
