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module shiyan01 (iclk,rst,oclk);
input iclk;
input rst;
output [5:0]oclk;
reg [15:0]counter;
reg [5:0]off;
reg [15:0]pwmwidth;
reg [15:0]pwmperiod;
reg [2:0]counter1;
reg clk;
always @ (posedge iclk or negedge rst)
begin
if(!rst)
begin
counter<=0;
pwmperiod<=16'b1000000000000000;
end
else
begin
if(counter>=pwmperiod-1)
counter<=0;
else
counter<=counter+1;
end
end
always @ (posedge iclk or negedge rst)
begin
if(!rst)
pwmwidth<=16'b0000000100000000;
else
begin
if(counter>=pwmwidth)
off<=6'b111111;
else
off<=6'b000000;
end
end
assign oclk=off;
endmodule
为什么我写的这个程序的输出一直是0,没有形成波形呢? |
阿莫论坛20周年了!感谢大家的支持与爱护!!
该献的血还是要献的。你不献他不献。难道让我去献? --- 出自坛友:lovejp1981
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