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module horse_light (clk,reset,led);
input clk,reset;
output reg [7:0] led;
reg [9:0] count;
reg [2:0] state;
parameter s0=0;
parameter s1=1;
parameter s2=2;
parameter s3=3;
parameter s4=4;
parameter s5=5;
parameter s6=6;
parameter s7=7;
always @ (posedge clk)
if(reset)
begin
state<=s0;
count<=10'b0;
end
else
case(state)
s0:if(count==10'b1111_1111_11)
begin
state<=s1;
count<=10'b0;
end
else
begin
led<=8'b0000_0001;
count<=count+1;
end
s1:if(count==10'b1111_1111_11)
begin
state<=s2;
count<=10'b0;
end
else
begin
led<=8'b0000_0010;
count<=count+1;
end
s2:if(count==10'b1111_1111_11)
begin
state<=s3;
count<=10'b0;
end
else
begin
led<=8'b0000_0100;
count<=count+1;
end
s3:if(count==10'b1111_1111_11)
begin
state<=s4;
count<=10'b0;
end
else
begin
led<=8'b0000_1000;
count<=count+1;
end
s4:if(count==10'b1111_1111_11)
begin
state<=s5;
count<=10'b0;
end
else
begin
led<=8'b0001_0000;
count<=count+1;
end
s5:if(count==10'b1111_1111_11)
begin
state<=s6;
count<=10'b0;
end
else
begin
led<=8'b0010_0000;
count<=count+1;
end
s6:if(count==10'b1111_1111_11)
begin
state<=s7;
count<=10'b0;
end
else
begin
led<=8'b0100_0000;
count<=count+1;
end
s7:if(count==10'b1111_1111_11)
begin
state<=s0;
count<=10'b0;
end
else
begin
led<=8'b1000_0000;
count<=count+1;
end
default:state<=s0;
endcase
endmodule |
阿莫论坛20周年了！感谢大家的支持与爱护！！
知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2009-11-9 10:08:39
楼主
