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楼主 |
发表于 2009-3-27 21:40:58
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欧，群里有人告诉我了，
首先用MDK的LPC2200头文件是对的
再次要在Power Control for Peripherals register (PCONP)要设置位10(PSPI1)和位23（PCSSP），复位默认是SPI1方式
Remark: Setting this bit to 1 and bit 10 (PSPI1) to 0, selects the SPI1
interface as SSP interface. At reset, SPI1 is enabled.
补充一下
While the SSP and SPI1 peripherals share the same physical pins, it is not possible to
have both of these two peripherals active at the same time. Bit 10 (PSPI1) and bit 21
(PSSP) residing in the Section 6–10.3 control the activity of the SPI1 and SSP module
respectively. The corresponding peripheral is enabled when its control bit is 1, and it is
disabled when the control bit is 0. After power-on reset, SPI1 is enabled, maintaining the
backward compatibility with other NXP LPC2000 microcontrollers. Any attempt to write 1
to PSPI1 and PSSP bits at the same time will result in PSPI = 1 and PSSP = 0.
To switch on the fly from SPI1 to SSP and back, first disable the active peripheral’s
interrupt(s), both in the peripheral’s and VIC’s registers. Next, clear all pending interrupt
flags (if any set). Only then, the currently enabled peripheral can be turned off in the
PCONP register. After this, the other serial interface can be enabled.
It is important to disable the currently used peripheral by clearing its bit in the PCONP
register only at the very end of the peripheral’s shut-down procedure. Otherwise, having 0
in a bit in PCONP will disable all clocks from coming into the peripheral controlled by that
bit. Then, reading from the peripheral’s registers will not yield valid data and write and/or
modify access will be banned, i.e. no content can be changed. Consequently, if any of the
interrupt triggering flags are left active in the peripheral’s register(s) when the peripheral is
disabled via the PCONP, the invoked ISR may not be able to successfully service pending
interrupt, and the same interrupt may keep overloading the microcontroller even though its
peripheral is disabled. |
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发表于 2009-3-27 21:30:27
