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求助：CC2430进入不了RF和DMA中断。
程序是如果在同信道有包发送，测试一下能否进入RF和DMA中断，至少应该可以进入RF SFD中断。
初学CC2430，不知道问题出在那里。
#define DMA_RX_CHINNEL 0 //RFRX DMA 通道0
#define DMA_TX_CHINNEL 1 //RFTX DMA 通道1
static DMA_DESC DMA_RX_DESC; // DMX RX 控制结构体
static DMA_DESC DMA_TX_DESC; // DMA TX 控制结构体
int main()
{
__disable_interrupt();
RF_Init(18,0,0); //18信道
__enable_interrupt();
while(1)
{
}
}
#pragma vector=RF_VECTOR
__interrupt static void rf_IRQ(void)
{
INT_GLOBAL_ENABLE(INT_OFF); //关闭总中断
RFIF = 0x00; // 清除RF 子中断标志位
INT_SETFLAG(INUM_RF, INT_CLR); //清除RF 通用中断标志位
INT_GLOBAL_ENABLE(INT_ON);
}
#pragma vector=DMA_VECTOR
__interrupt void dma_IRQ (void)
{
INT_GLOBAL_ENABLE(INT_OFF);
DMAIF = 0;
DMAIRQ= 0;
INT_GLOBAL_ENABLE(INT_ON);
}
void RF_Init(uint8 chinnel,uint8 addr_h,uint8 addr_l) //初始化RF,并进入接收状态
{
HARD_ADDR[0]=addr_h; //设置地址
HARD_ADDR[1]=addr_l; //设置地址
memset((void*) &DMA_TX_DESC, 0, sizeof( DMA_TX_DESC)); //清零DMA TX 控制结构体
memset((void*) &DMA_RX_DESC, 0, sizeof( DMA_RX_DESC)); //清零DMA RX 控制结构体
DMAARM = 0;
DMAREQ = 0;
DMAIRQ = 0;
culDmaToRadio(&DMA_TX_DESC, 255, (void *)&PacketSend, TRUE);
//设置DMA通道关联到 RF TX
//TX DMA由手动触发
culDmaFromRadio(&DMA_RX_DESC, (void *)&PacketRecv, TRUE);
//设置DMA通道关联到 RF TX，
//RX DMA由 RF接收包触发
DMA0CFGH=(uint16)(&DMA_RX_DESC)/256; //设置DMA通道0 控制结构体地址
DMA0CFGL=(uint16)(&DMA_RX_DESC)%256;
DMA1CFGH=(uint16)(&DMA_TX_DESC)/256; //设置DMA通道1 控制结构体地址
DMA1CFGL=(uint16)(&DMA_TX_DESC)%256;
DMA_ABORT_CHANNEL(DMA_RX_CHINNEL); //DMA通道停止,并装载DMA RX配置
INT_SETFLAG(INUM_DMA, INT_CLR); //清除 DMA中断标志位
INT_ENABLE(INUM_DMA, INT_ON); //打开DMA中断
RFIF = 0; //清除RF中断标志
RFIM = 0; //禁止所有RF中断
halRfConfig(((chinnel-10)*5+2400)*1000); //设置信道频率
IOCFG0 = 7; //设置RX FIFO 阈值
TXCTRLL = 0xE7; //发射功率 -15 dbm
INT_SETFLAG(INUM_RF,INT_CLR); //清除RF总中断标志
INT_ENABLE(INUM_RF,INT_ON); //打开RF中断
INT_SETFLAG(INUM_RFERR, INT_CLR); //清除RF ERR中断标志
INT_ENABLE(INUM_RFERR, INT_ON); //打开RF ERR中断
RFIM = IRQ_SFD |IRQ_TXDONE |IRQ_FIFOP; //允许RF SFD,TXDONE和FIFOP中断
SRXON; //使能RX和频率校准合成器+
SFLUSHTX; //清空 TX FIFO
SFLUSHRX; //清空 RX FIFO ,复位解调器
SFLUSHRX; //清空 RX FIFO ,复位解调器
STXCALN; //使能 TX 频率校准合成器
ISSTART; //开始运行
}
void culDmaToRadio(DMA_DESC* pDmaChannel, WORD length, BYTE* pSrcAddr, BOOL generateInterrupt)
{
SET_WORD(pDmaChannel->SRCADDRH, pDmaChannel->SRCADDRL, pSrcAddr); // The start address of the segment
SET_WORD(pDmaChannel->DESTADDRH, pDmaChannel->DESTADDRL, &X_RFD); // Tx FIFO address
SET_WORD(pDmaChannel->LENH, pDmaChannel->LENL, length); // Setting the length of the transfer (bytes)
pDmaChannel->VLEN = VLEN_USE_LEN; // Using the length field
pDmaChannel->PRIORITY = PRI_HIGH; // High priority
pDmaChannel->M8 = M8_USE_8_BITS; // Transferring all 8 bits in each byte.
pDmaChannel->IRQMASK = generateInterrupt; // The DMA complete interrupt flag is set at completion.
pDmaChannel->DESTINC = DESTINC_0; // DMA 写目的地址固定
pDmaChannel->SRCINC = SRCINC_1; // DMA 读地址 每次加1
// after each transfer.
pDmaChannel->TRIG = DMATRIG_NONE; // DMA is started by writing the DMAREQ register.
pDmaChannel->TMODE = TMODE_BLOCK; // The whole block is transferred.
pDmaChannel->WORDSIZE = WORDSIZE_BYTE; // One byte is transferred each time.
return;
}
void culDmaFromRadio(DMA_DESC* pDmaChannel, BYTE *pDstAddr, BOOL generateInterrupt)
{
SET_WORD(pDmaChannel->SRCADDRH, pDmaChannel->SRCADDRL, &X_RFD); // The start address of the segment
SET_WORD(pDmaChannel->DESTADDRH, pDmaChannel->DESTADDRL, pDstAddr); // Tx FiFo address
SET_WORD(pDmaChannel->LENH, pDmaChannel->LENL, 255); // Maximum of the Tx FiFo.
pDmaChannel->VLEN = VLEN_1_P_VALOFFIRST;// The first byte indicates transfer length
pDmaChannel->PRIORITY = PRI_HIGH;
pDmaChannel->M8 = M8_USE_7_BITS;
pDmaChannel->IRQMASK = generateInterrupt; // The DMA complete interrupt flag is set at completion.
pDmaChannel->DESTINC = DESTINC_1; // The destination is constant
pDmaChannel->SRCINC = SRCINC_0; // The address for data fetch is incremented by 1 byte after each transfer.
pDmaChannel->TRIG = DMATRIG_RADIO; // DMA 由RF 接受包触发
pDmaChannel->TMODE = TMODE_SINGLE; // One byte is transferred at each DMA trigger.
pDmaChannel->WORDSIZE = WORDSIZE_BYTE; // Byte transfer.
return;
} |
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发表于 2008-8-14 11:02:18
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