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最近在学习状态机，从我入门的特权同学和黑金开发板入手，对比了一下两种代码风格。。。。
特权同学的一段式状态机：
module state_machine(
clk,
rst_n,
cmd,
wr_req,
rd_req
);
input clk;
input rst_n;
output [3:0] cmd;
input rd_req;
input wr_req;
reg [3:0] cmd;
reg [3:0] cstate;
parameter IDLE = 0,
WR_S1 = 1,
WR_S2 = 2,
RD_S1 = 3,
RD_S2 = 4;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cstate <= IDLE;
cmd <= 3'b111;
end
else
case(cstate)
IDLE:
if(wr_req) begin
cstate <= WR_S1;
cmd <= 3'b011;
end
else if(rd_req)begin
cstate <= RD_S1;
cmd <= 3'b011;
end
else begin
cstate <= IDLE;
cmd <= 3'b111;
end
WR_S1:begin
cstate <= WR_S2;
cmd <= 3'b101;
end
WR_S2:begin
cstate <= IDLE;
cmd <= 3'b111;
end
RD_S1:
if(wr_req) begin
cstate <= WR_S2;
cmd <= 3'b101;
end
else begin
cstate <= RD_S2;
cmd <= 3'b110;
end
RD_S2:
if(wr_req) begin
cstate <= WR_S1;
cmd <= 3'b011;
end
else begin
cstate <= IDLE;
cmd <= 3'b111;
end
default: cstate <= IDLE;
endcase
end
endmodule
下面是黑金开发板提供的类状态机写法：
module state_machine(
clk,
rst_n,
cmd,
wr_req,
rd_req
);
input clk;
input rst_n;
output [3:0] cmd;
input rd_req;
input wr_req;
reg [3:0] cmd;
reg [3:0] i;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
i <= 4'd0;
cmd <= 3'b111;
end
else
case(i)
4'd0:
if(wr_req) begin
i <= i + 1'd1;
cmd <= 3'b011;
end
else if(rd_req)begin
i <= 4'd3;
cmd <= 3'b011;
end
else begin
i <= 4'd0;
cmd <= 3'b111;
end
4'd1:begin
i <= i + 1'd1;
cmd <= 3'b101;
end
4'd2:begin
i <= 4'd0;
cmd <= 3'b111;
end
4'd3:
if(wr_req) begin
i <= 4'd1;
cmd <= 3'b101;
end
else begin
i <= i +1'd1;
cmd <= 3'b110;
end
4'd4:
if(wr_req) begin
i <= 4'd1;
cmd <= 3'b011;
end
else begin
i <= 4'd0;
cmd <= 3'b111;
end
default: i <= 4'd0;
endcase
end
endmodule
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发表于 2013-9-26 10:45:40
楼主
