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楼主 |
发表于 2013-6-4 14:50:28
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紫风幻月 发表于 2013-6-3 08:32 
我也想过 不过不知怎加；你有思路吗？
定制好ROM了 数据存进去了 怎么液晶一点反应都没有 谁能看看怎么回事？
module lcd(clock,rst_n,rs,rw,en,data,psb);
input clock; //system clock,50MHz
input rst_n; //global reset, low level effective
output rs; //LCD Command/Data select,0=Command,1=Data
output rw;//LCD Read/Write Select,0=Write,1=Read
output en;//LCD Enable,fail edge effective
output [7:0] data;//8-bit LCD DATA
output psb;
//wire
assign psb = 1'b1;
assign rw = 1'b1; //LCD Write mode
//---------------------------------------------------------
// Produce 0.5KHz(2ms) clock
//---------------------------------------------------------
reg lcd_clock; //20KHz clock
reg [11:0] lcd_cnt; //count
always@(posedge clock or negedge rst_n)
begin
if(!rst_n) //reset
begin
lcd_cnt <= 12'd0;
lcd_clock <= 1'b0;
end
else if(lcd_cnt == 12'd2499)//50us
begin
lcd_cnt <= 12'd0;
lcd_clock <= ~ lcd_clock; //50us turn,20KHz
end
else
lcd_cnt <= lcd_cnt +1'b1;
end
//---------------------------------------------------------
// Parameter set
//---------------------------------------------------------
parameter IDLE = 4'd0; //initial
parameter SETMODE = 4'd1; //entry mode set
parameter SWITCHMODE = 4'd2; //display status
parameter SETFUNCTION0 = 4'd3; //function set
parameter SETFUNCTION1 = 4'd4; //function set
parameter DISPLAY0 = 4'd5; //Y coord set
parameter DISPLAY1 = 4'd6; //X coord set
parameter WRITERAM = 4'd7; //write
parameter STOP = 4'd8; //stop
parameter CLEAR = 4'd9; //clear
//---------------------------------------------------------
// LCD Read or Write Select
//---------------------------------------------------------
reg [3:0] state;//state
reg rs;//LCD Command/Data select,0=Command,1=Data
//Only write data, the rs will be high level, other is low level
always @(posedge lcd_clock or negedge rst_n)
begin
if(!rst_n)
rs <= 1'b0; //reset, command mode
else if(state == WRITERAM)
rs <= 1'b1; //start write, data mode
else
rs <= 1'b0; //finish write, command mode
end
reg flag; //flag, LCD12864 operate finish with low level
assign en = (flag == 1)?lcd_clock:1'b0;
//---------------------------------------------------------
// State machine
//---------------------------------------------------------
reg [9:0] cnt; //coord count
reg [7:0] data; //8-bit LCD DATA
wire [7:0] data_disp; //display data
always@(posedge lcd_clock or negedge rst_n)
begin
if(!rst_n) //reset
begin
state <= IDLE;
data <= 8'bzzzz_zzzz;
flag <= 1'b1;
cnt <= 10'd0;
end
else
begin
case(state)
//************************start****************************
IDLE :
begin
state <= SETFUNCTION0;
data <= 8'bzzzz_zzzz;
flag <= 1'b1;
cnt <= 10'd0;
end
//************************ function set ********************
SETFUNCTION0 : begin
data <= 8'h30;//8 bit MPU port
state <= SETMODE ;//basic instruction set
end
//************************ set mode ************************
SETMODE : //cursor move to the right
begin //DDRAM address count add 1
data <= 8'h06; //frame
state <= CLEAR;
end
CLEAR:
begin
data<=8'h01;
state<=SWITCHMODE;
end
//************************ switch mode**********************
SWITCHMODE : //display on
begin //cursor display off
data <= 8'h0c; //glint display off
state <= SETFUNCTION1;
end
//*********************** function set *********************
SETFUNCTION1 :
begin
data <= 8'h36;//8 bit MPU port
state <= DISPLAY0;//expanded instruction set
end
//*********************** Y coord set **********************
DISPLAY0 :
begin
data <= {3'b100,cnt[8:4]};
state <= DISPLAY1;
end
//*********************** X coord set ***********************
DISPLAY1 :
begin
data <= {4'd8,cnt[9],3'd0};
state <= WRITERAM;
end
//**********************writeram**************************
WRITERAM :
begin
data <= data_disp;
cnt <= cnt + 1'b1;
if(line_done)
begin
if(frame_done)
state <= STOP;//screen finish
else
state <= DISPLAY0;//line finish
end
else
state <= WRITERAM;
end
//********************** stop******************************
STOP :
begin
state <= STOP;
flag <= 1'b0;
end
default: state <= IDLE;
endcase
end
end
assign line_done = (cnt[3:0] == 4'hf);//line finish
assign frame_done = (cnt[9:4] == 7'h3f);//screen finish
//---------------------------------------------------------// RAM
//---------------------------------------------------------
rom rom (.address (cnt),.clock (clock),.q (data_disp));
endmodule |
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发表于 2013-5-29 08:42:08
