|
用verilog 写了一个代码,综合时提示:
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
这是用xilinx ise综合时提示的错误,实际代码300多行,程序实现一个96个IO的双向控制 ,程序比较简单
Macrocells Used Pterms Registers Used Pins Used Function Block Inputs Used
97/288 (34%) 532/1440 (37%) 97/288 (34%) 103/168 (62%) 507/576 (89%)
请教一下这是什么问题?
具体程序如下:
module spi (rst,clk,
sdi,sdo,sck,cs,cmd,
port0,port1,port2,port3,port4,port5,port6,port7,port8,port9,port10,port11,
);
input rst; // 异步清零
input sdi; // spi data input
input sck; // spi clk, MAX 25MHz
input cs; // spi enable
input clk; // cpld main clk,MIN 50MHz
input cmd; // command reg or dat
inout [7:0]port0; // 8bit Data,configure input or output default status:input
inout [7:0]port1;
inout [7:0]port2;
inout [7:0]port3;
inout [7:0]port4;
inout [7:0]port5;
inout [7:0]port6;
inout [7:0]port7;
inout [7:0]port8;
inout [7:0]port9;
inout [7:0]port10;
inout [7:0]port11;
output reg sdo; // spi data output
reg [1:0]receive_flag;
reg wsdi;
reg Bwsck;
reg wcs;
reg wsck;
reg command; // 0:read data 1:read bit 2:write byte 3:write bit
reg[1:0] status;
reg[7:0] count;
reg[7:0] receiver_data;
reg[23:0]receiver_cmd;
reg[7:0] send_buff;
reg[95:0]en; //3态使能
reg[7:0] en_bit;
reg[7:0] port_reg;
reg[7:0] port_bit;
reg[95:0]port_value; //端口缓存
assign port0[0]=en[0]? port_value[0]:1'bz; //默认高阻态
assign port0[1]=en[1]? port_value[1]:1'bz;
assign port0[2]=en[2]? port_value[2]:1'bz;
assign port0[3]=en[3]? port_value[3]:1'bz;
assign port0[4]=en[4]? port_value[4]:1'bz;
assign port0[5]=en[5]? port_value[5]:1'bz;
assign port0[6]=en[6]? port_value[6]:1'bz;
assign port0[7]=en[7]? port_value[7]:1'bz;
assign port1[0]=en[8] ?port_value[8]:1'bz;
assign port1[1]=en[9] ?port_value[9]:1'bz;
assign port1[2]=en[10]?port_value[10]:1'bz;
assign port1[3]=en[11]?port_value[11]:1'bz;
assign port1[4]=en[12]?port_value[12]:1'bz;
assign port1[5]=en[13]?port_value[13]:1'bz;
assign port1[6]=en[14]?port_value[14]:1'bz;
assign port1[7]=en[15]?port_value[15]:1'bz;
assign port2[0]=en[16]?port_value[16]:1'bz;
assign port2[1]=en[17]?port_value[17]:1'bz;
assign port2[2]=en[18]?port_value[18]:1'bz;
assign port2[3]=en[19]?port_value[19]:1'bz;
assign port2[4]=en[20]?port_value[20]:1'bz;
assign port2[5]=en[21]?port_value[21]:1'bz;
assign port2[6]=en[22]?port_value[22]:1'bz;
assign port2[7]=en[23]?port_value[23]:1'bz;
assign port3[0]=en[24]?port_value[24]:1'bz;
assign port3[1]=en[25]?port_value[25]:1'bz;
assign port3[2]=en[26]?port_value[26]:1'bz;
assign port3[3]=en[27]?port_value[27]:1'bz;
assign port3[4]=en[28]?port_value[28]:1'bz;
assign port3[5]=en[29]?port_value[29]:1'bz;
assign port3[6]=en[30]?port_value[30]:1'bz;
assign port3[7]=en[31]?port_value[31]:1'bz;
assign port4[0]=en[32]?port_value[32]:1'bz;
assign port4[1]=en[33]?port_value[33]:1'bz;
assign port4[2]=en[34]?port_value[34]:1'bz;
assign port4[3]=en[35]?port_value[35]:1'bz;
assign port4[4]=en[36]?port_value[36]:1'bz;
assign port4[5]=en[37]?port_value[37]:1'bz;
assign port4[6]=en[38]?port_value[38]:1'bz;
assign port4[7]=en[39]?port_value[39]:1'bz;
assign port5[0]=en[40]?port_value[40]:1'bz;
assign port5[1]=en[41]?port_value[41]:1'bz;
assign port5[2]=en[42]?port_value[42]:1'bz;
assign port5[3]=en[43]?port_value[43]:1'bz;
assign port5[4]=en[44]?port_value[44]:1'bz;
assign port5[5]=en[45]?port_value[45]:1'bz;
assign port5[6]=en[46]?port_value[46]:1'bz;
assign port5[7]=en[47]?port_value[47]:1'bz;
assign port6[0]=en[48]?port_value[48]:1'bz;
assign port6[1]=en[49]?port_value[49]:1'bz;
assign port6[2]=en[50]?port_value[50]:1'bz;
assign port6[3]=en[51]?port_value[51]:1'bz;
assign port6[4]=en[52]?port_value[52]:1'bz;
assign port6[5]=en[53]?port_value[53]:1'bz;
assign port6[6]=en[54]?port_value[54]:1'bz;
assign port6[7]=en[55]?port_value[55]:1'bz;
assign port7[0]=en[56]?port_value[56]:1'bz;
assign port7[1]=en[57]?port_value[57]:1'bz;
assign port7[2]=en[58]?port_value[58]:1'bz;
assign port7[3]=en[59]?port_value[59]:1'bz;
assign port7[4]=en[60]?port_value[60]:1'bz;
assign port7[5]=en[61]?port_value[61]:1'bz;
assign port7[6]=en[62]?port_value[62]:1'bz;
assign port7[7]=en[63]?port_value[63]:1'bz;
assign port8[0]=en[64]?port_value[64]:1'bz;
assign port8[1]=en[65]?port_value[65]:1'bz;
assign port8[2]=en[66]?port_value[66]:1'bz;
assign port8[3]=en[67]?port_value[67]:1'bz;
assign port8[4]=en[68]?port_value[68]:1'bz;
assign port8[5]=en[69]?port_value[69]:1'bz;
assign port8[6]=en[70]?port_value[70]:1'bz;
assign port8[7]=en[71]?port_value[71]:1'bz;
assign port9[0]=en[72]?port_value[72]:1'bz;
assign port9[1]=en[73]?port_value[73]:1'bz;
assign port9[2]=en[74]?port_value[74]:1'bz;
assign port9[3]=en[75]?port_value[75]:1'bz;
assign port9[4]=en[76]?port_value[76]:1'bz;
assign port9[5]=en[77]?port_value[77]:1'bz;
assign port9[6]=en[78]?port_value[78]:1'bz;
assign port9[7]=en[79]?port_value[79]:1'bz;
assign port10[0]=en[80]?port_value[80]:1'bz;
assign port10[1]=en[81]?port_value[81]:1'bz;
assign port10[2]=en[82]?port_value[82]:1'bz;
assign port10[3]=en[83]?port_value[83]:1'bz;
assign port10[4]=en[84]?port_value[84]:1'bz;
assign port10[5]=en[85]?port_value[85]:1'bz;
assign port10[6]=en[86]?port_value[86]:1'bz;
assign port10[7]=en[87]?port_value[87]:1'bz;
assign port11[0]=en[88]?port_value[88]:1'bz;
assign port11[1]=en[89]?port_value[89]:1'bz;
assign port11[2]=en[90]?port_value[90]:1'bz;
assign port11[3]=en[91]?port_value[91]:1'bz;
assign port11[4]=en[92]?port_value[92]:1'bz;
assign port11[5]=en[93]?port_value[93]:1'bz;
assign port11[6]=en[94]?port_value[94]:1'bz;
assign port11[7]=en[95]?port_value[95]:1'bz;
always@(posedge clk)
begin
wsdi <= sdi;
wsck <= sck;
wcs <= cs;
command<=cmd;
end
always@(posedge clk)
begin
Bwsck <= wsck;
end
always@(posedge clk or negedge rst or posedge wcs)
begin
if(!rst)
begin
count<=1'b0;
sdo <= 1'b0;
en <=8'h00;
receive_flag<=2'b00;
end
else if(wcs)
begin
sdo <= 1'b0;
count<=1'b0;
end
else if(wsck && (!Bwsck)) //上升沿处理 SPI
begin
if(command==1'b1) //receive command
begin
if(count==8'h17) //3byte
begin
count<=1'b0;
receiver_cmd<={receiver_cmd[22:0],wsdi}; //receiver[23:16] port select
receive_flag<=1'b1; //receiver[15:8] bit select
send_buff[7:0]<=8'h00; //receiver[7:0] read and write status control
end
else
begin
count<=count+1'b1;
receiver_cmd<={receiver_cmd[22:0],wsdi};
end
end
else if(command==1'b0) //receive data
begin
if(count==4'h7)
begin
count<=1'b0;
receiver_data<=1'b0;
receiver_data <={receiver_data[6:0],wsdi};
receive_flag<=2'b10;
end
else
begin
count<=count+1'b1;
receiver_data <={receiver_data[6:0],wsdi};
end
end
end
else if(receive_flag==1'b1) //command process
begin
receive_flag<=1'b0;
case(receiver_cmd[7:0])
8'h00: //read byte
begin
case(receiver_cmd[23:16])
8'h00:begin en[7:0] <=8'h00; end
8'h01:begin en[15:8]<=8'h00; end
8'h02:begin en[23:16]<=8'h00; end
8'h03:begin en[31:24]<=8'h00; end
8'h04:begin en[39:32]<=8'h00; end
8'h05:begin en[47:40]<=8'h00; end
8'h06:begin en[55:48]<=8'h00; end
8'h07:begin en[63:56]<=8'h00; end
8'h08:begin en[71:64]<=8'h00; end
8'h09:begin en[79:72]<=8'h00; end
8'h0a:begin en[87:80]<=8'h00; end
8'h0b:begin en[95:88]<=8'h00; end
endcase
status<=1'b0;
end
8'h01: //read bit
begin
case(receiver_cmd[23:16])
8'h00:begin en_bit<=8'd00; port_reg<=port0; end
8'h01:begin en_bit<=8'd08; port_reg<=port1; end
8'h02:begin en_bit<=8'd16; port_reg<=port2; end
8'h03:begin en_bit<=8'd24; port_reg<=port3; end
8'h04:begin en_bit<=8'd32; port_reg<=port4; end
8'h05:begin en_bit<=8'd40; port_reg<=port5; end
8'h06:begin en_bit<=8'd48; port_reg<=port6; end
8'h07:begin en_bit<=8'd56; port_reg<=port7; end
8'h08:begin en_bit<=8'd64; port_reg<=port8; end
8'h09:begin en_bit<=8'd72; port_reg<=port9; end
8'h0a:begin en_bit<=8'd80; port_reg<=port10;end
8'h0b:begin en_bit<=8'd88; port_reg<=port11;end
endcase
status<=1'b1;
end
8'h02: //write byte
begin
case(receiver_cmd[23:16])
8'h00:begin en[7:0] <=8'hff; end
8'h01:begin en[15:8]<=8'hff; end
8'h02:begin en[23:16]<=8'hff; end
8'h03:begin en[31:24]<=8'hff; end
8'h04:begin en[39:32]<=8'hff; end
8'h05:begin en[47:40]<=8'hff; end
8'h06:begin en[55:48]<=8'hff; end
8'h07:begin en[63:56]<=8'hff; end
8'h08:begin en[71:64]<=8'hff; end
8'h09:begin en[79:72]<=8'hff; end
8'h0a:begin en[87:80]<=8'hff; end
8'h0b:begin en[95:88]<=8'hff; end
endcase
status<=2'b10;
end
8'h03: //write_bit
begin
case(receiver_cmd[23:16])
8'h00:begin en_bit<=8'd00; port_reg<=port0; end
8'h01:begin en_bit<=8'd08; port_reg<=port1; end
8'h02:begin en_bit<=8'd16; port_reg<=port2; end
8'h03:begin en_bit<=8'd24; port_reg<=port3; end
8'h04:begin en_bit<=8'd32; port_reg<=port4; end
8'h05:begin en_bit<=8'd40; port_reg<=port5; end
8'h06:begin en_bit<=8'd48; port_reg<=port6; end
8'h07:begin en_bit<=8'd56; port_reg<=port7; end
8'h08:begin en_bit<=8'd64; port_reg<=port8; end
8'h09:begin en_bit<=8'd72; port_reg<=port9; end
8'h0a:begin en_bit<=8'd80; port_reg<=port10;end
8'h0b:begin en_bit<=8'd88; port_reg<=port11;end
endcase
status<=2'b11;
end
endcase
end
else if(receive_flag==2'b10) //data process
begin
receive_flag<=1'b0;
if(status==1'b0) //send byte
begin
case(receiver_cmd[23:16])
8'h00:begin send_buff<=port0; end
8'h01:begin send_buff<=port1; end
8'h02:begin send_buff<=port2; end
8'h03:begin send_buff<=port3; end
8'h04:begin send_buff<=port4; end
8'h05:begin send_buff<=port5; end
8'h06:begin send_buff<=port6; end
8'h07:begin send_buff<=port7; end
8'h08:begin send_buff<=port8; end
8'h09:begin send_buff<=port9; end
8'h0a:begin send_buff<=port10; end
8'h0b:begin send_buff<=port11; end
endcase
status<=1'b0;
end
else if(status==1'b1) //send bit
begin
case(receiver_cmd[15:8])
8'h00:begin en[en_bit]<=1'b0; send_buff<={send_buff[6:0],port_reg[0]};end
8'h01:begin en[en_bit+1]<=1'b0; send_buff<={send_buff[6:0],port_reg[1]};end
8'h02:begin en[en_bit+2]<=1'b0; send_buff<={send_buff[6:0],port_reg[2]};end
8'h03:begin en[en_bit+3]<=1'b0; send_buff<={send_buff[6:0],port_reg[3]};end
8'h04:begin en[en_bit+4]<=1'b0; send_buff<={send_buff[6:0],port_reg[4]};end
8'h05:begin en[en_bit+5]<=1'b0; send_buff<={send_buff[6:0],port_reg[5]};end
8'h06:begin en[en_bit+6]<=1'b0; send_buff<={send_buff[6:0],port_reg[6]};end
8'h07:begin en[en_bit+7]<=1'b0; send_buff<={send_buff[6:0],port_reg[7]};end
endcase
status<=1'b0;
end
else if(status==2'b10) //write byte process
begin
case(receiver_cmd[23:16])
8'h00:begin port_value[7:0] <=receiver_data; end
8'h01:begin port_value[15:8] <=receiver_data; end
8'h02:begin port_value[23:16]<=receiver_data; end
8'h03:begin port_value[31:24]<=receiver_data; end
8'h04:begin port_value[39:32]<=receiver_data; end
8'h05:begin port_value[47:40]<=receiver_data; end
8'h06:begin port_value[55:48]<=receiver_data; end
8'h07:begin port_value[63:56]<=receiver_data; end
8'h08:begin port_value[71:64]<=receiver_data; end
8'h09:begin port_value[79:72]<=receiver_data; end
8'h0a:begin port_value[87:80]<=receiver_data; end
8'h0b:begin port_value[95:88]<=receiver_data; end
endcase
status<=1'b0;
end
else if(status==2'b11) //write bit process
begin
case(receiver_cmd[15:8])
8'h00:begin port_value[port_bit] <=receiver_data[0];end
8'h01:begin port_value[port_bit+1]<=receiver_data[0];end
8'h02:begin port_value[port_bit+2]<=receiver_data[0];end
8'h03:begin port_value[port_bit+3]<=receiver_data[0];end
8'h04:begin port_value[port_bit+4]<=receiver_data[0];end
8'h05:begin port_value[port_bit+5]<=receiver_data[0];end
8'h06:begin port_value[port_bit+6]<=receiver_data[0];end
8'h07:begin port_value[port_bit+7]<=receiver_data[0];end
endcase
status<=1'b0;
end
end
else if(command==1'b0) // send port data to mcu
begin
sdo<=send_buff[7-count];
end
else if(command==1'b1)
begin
sdo<=1'b0;
end
end
endmodule
|
阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
|