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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hb is
Port ( sysclk : in std_logic;
-- ena : in std_logic;
enclk : out std_logic;
daclk : out std_logic;
datain : in std_logic_vector(7 downto 0);
--dataine : out std_logic_vector(15 downto 0);
-- sampleclk1 : in std_logic; ------------------------------------------
--sampleclk1 is 10.28K
-- sampleclk2 : in std_logic; ---------------------------------------------
--sampleclk2 is 10.28*256=2.63
dataout : out std_logic_vector(11 downto 0)); -------------------------------15
end hb;
architecture Behavioral of hb is
component pll is
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
---------------rclock signals is added here
----------------
signal datainext : std_logic_vector(27 downto 0);--29
signal acca : std_logic_vector(27 downto 0); ---29
signal enclk_temp: std_logic;
signal daclk_temp: std_logic;
signal clk_50M : STD_LOGIC;
signal accb : std_logic_vector(27 downto 0);--24
--signal accb_delay : std_logic_vector(27 downto 0);
signal accc : std_logic_vector(27 downto 0);
--signal accc_delay :std_logic_vector(27 downto 0);
signal accd : std_logic_vector(27 downto 0);
signal accd_delay :std_logic_vector(27 downto 0);
signal comb1: std_logic_vector(27 downto 0);--
--signal comb1e: std_logic_vector(17 downto 0);--
signal comb1_delay: std_logic_vector(27 downto 0);--13
signal comb2: std_logic_vector(27 downto 0); ---
signal comb2_delay: std_logic_vector(27 downto 0);--12
signal comb3: std_logic_vector(27 downto 0);--12
signal comb3_delay: std_logic_vector(27 downto 0);
signal comb4: std_logic_vector(27 downto 0);
signal comb4_delay: std_logic_vector(27 downto 0);
signal decimate_count: std_logic_vector(3 downto 0);
begin
--------------------produce sampleclk1 and sampleclk2
---------------------------------
-----------------rcic filter
--------------------------------
datainext(27)<=datain(7);
datainext(26)<=datain(7);
datainext(25)<=datain(7);
datainext(24)<=datain(7);
datainext(23)<=datain(7);
datainext(22)<=datain(7);
datainext(21)<=datain(7);
datainext(20)<=datain(7);
datainext(19)<=datain(7);
datainext(18)<=datain(7);
datainext(17)<=datain(7);
datainext(16)<=datain(7);
datainext(15)<=datain(7);
datainext(14)<=datain(7);
datainext(13)<=datain(7);
datainext(12)<=datain(7);
datainext(11)<=datain(7);
datainext(10)<=datain(7);
datainext(9)<=datain(7);
datainext(8)<=datain(7);
datainext(7 downto 0)<=datain(7 downto 0);
dataout<=comb4(27 downto 16);---(29 downto 14);
--enclk_temp<=sysclk;
--daclk_temp<=sysclk;
enclk <= clk_50M;
daclk <= clk_50M;
--dataine<=datain&"0000";
process (clk_50M)
begin
if clk_50M='1' and clk_50M'event then
decimate_count<=decimate_count+1;
-- if sampleclk2='1' then
acca<=acca+datainext;
-- acca_delay<=acca;
accb<=accb+acca;
accc<=accc+accb;
accd<=accd+accc;
if decimate_count="1111" then ---Decimation Ratio=16
accd_delay<=accd;
comb1_delay<=comb1;
comb2_delay<=comb2;
comb3_delay<=comb3;
comb1<=accd-accd_delay;
comb2<=comb1-comb1_delay;
comb3<=comb2-comb2_delay;
comb4<=comb3-comb3_delay;
end if;
end if;
end process;
u1:pll port map (inclk0=>sysclk,c0=>clk_50M);
end Behavioral;
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阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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