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- --moore状态机
- --**************库定义、 包定义********************
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- --**************实体定义********************
- entity moore IS
- port(
- clk,ready,read_write : in std_logic;
- reset : in std_logic;--复位输入
- oe,we : out std_logic
- );
- end moore;
- --**************构造体定义********************
- architecture state_machine of moore is
- type state_type is(idle,decision,read,write);--自定义信号类型
- signal present_state,next_state:state_type;
- begin
- state_comb : process(present_state,ready,read_write)
- begin
- case present_state is
- when idle=> --空闲状态
- oe<='1';
- we<='1';
- if ready='1' then
- next_state<=decision;
- else
- next_state<=idle;
- end if;
- when decision=> --判定状态
- oe<='0';
- we<='0';
- if read_write='1' then
- next_state<=read;
- else
- next_state<=write;
- end if;
- when read=> --读状态
- oe<='1';
- we<='0';
- if ready='1' then
- next_state<=idle;
- else
- next_state<=read;
- end if;
- when write=> --写状态
- oe<='0';
- we<='1';
- if ready='1' then
- next_state<=idle;
- else
- next_state<=write;
- end if;
- end case;
- end process state_comb;
- state_clocked: process(clk,reset)
- begin
- if(reset = '0') then
- present_state<=idle;
- elsif rising_edge(clk) then
- present_state<=next_state;
- end if;
- end process;
- end state_machine;
复制代码 下面是仿真前加入的信号,给reset两个复位信号,read_write一个低电平信号:
仿真结果:
前部分展开图:
比较疑惑的问题是,为何第二个reset信号完之后,后面就没有波形了,按住程序来说在还没到read_write的低电平来之前应该还重复前面的波形啊???
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