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发表于 2013-2-22 09:29:10
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kebaojun305 发表于 2013-2-22 08:09
肯定是你时序的问题 最大133M 我的 SDRAM 最大是166M 我用的频率是60M 读写都OK ...
哦,你用的是什么型号的sdram,我用了个mt48lc8m16a2仿真模型代替HY57V641620ETP的来modelsim仿真,出现如下错误提示,
Note : Cyclone IV E PLL was reset
# Time: 0 ns Instance: modelsim_test_tb.sdr_test.uut_sysctrl.uut_PLL_ctrl.altpll_component.cycloneiii_pll.pll3
# ** Error: E:/log/13.02.18/m3_232SDRAM3_1_many/mt48lc8m16a2.v(892): $hold( posedge Clk:260 ns, Cke:260 ns, 800 ps );
# Time: 260 ns Iteration: 6 Instance: /modelsim_test_tb/mt48lc8m16a2
# ** Error: E:/log/13.02.18/m3_232SDRAM3_1_many/mt48lc8m16a2.v(893): $hold( posedge Clk:260 ns, Cs_n:260 ns, 800 ps );
# Time: 260 ns Iteration: 6 Instance: /modelsim_test_tb/mt48lc8m16a2
# Note : Cyclone IV E PLL locked to incoming clock
# Time: 420 ns Instance: modelsim_test_tb.sdr_test.uut_sysctrl.uut_PLL_ctrl.altpll_component.cycloneiii_pll.pll3
# ** Error: E:/log/13.02.18/m3_232SDRAM3_1_many/mt48lc8m16a2.v(889): $width( negedge Clk:420 ns, :422187 ps, 2500 ps );
# Time: 422187 ps Iteration: 3 Instance: /modelsim_test_tb/mt48lc8m16a2
# ** Error: E:/log/13.02.18/m3_232SDRAM3_1_many/mt48lc8m16a2.v(890): $period( negedge Clk:420 ns, :427187 ps, 7500 ps );
# Time: 427187 ps Iteration: 3 Instance: /modelsim_test_tb/mt48lc8m16a2
# write data: 72
应该是 时序违例,你用仿真里没有,有没有仿真模型,给我个modelsim下? |
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