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发表于 2012-12-19 19:25:32
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看了文檔的說明, 主要你的想要找的答案在下:
The control interface module also contains a 16-bit down counter and control circuit that is used to generate periodic
refresh commands to the command module. The 16-bit down counter is loaded with the value from REG2 and counts
down to zero. The REFRESH_REQ output is asserted when the counter reaches zero and remains asserted until the
command module acknowledges the request. The acknowledge from the command module causes the down counter
to be reloaded with REG2 and the process repeats. REG2 is a 16-bit value that represents the period between
REFRESH commands that the SDR SDRAM Controller issues. The value is set by the equation
int(refresh_period/clock_period).
For example, if an SDRAM device that is connected to the SDR SDRAM Controller has a 64-ms, 4096-cycle refresh
requirement, the device must have a REFRESH command issued to it at least every
64 ms/4096 = 15.625 μs.
If the SDRAM and SDR SDRAM Controller are clocked by a 100-MHz clock, the maximum value of REG2 is
15.625 μs/0.01μs = 1562d.
只要你對REG2設定好刷新的數值後, 這個IP會自動幫你產生REFRESH Command. |
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