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楼主 |
发表于 2012-11-13 11:18:16
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这样吧,我先把我掌握的代码贡献出来!!
//
//module gray_grade(rst,pclk,vsync,link_i,link_o,row,lock,ser_clk,
module large_led(rst,pclk,link_i,link_o,row,lock,ser_clk,
en,oe,le,str,addr_arm,data_arm,ctr_arm,addr_l,
data_l,ctr_l,addr_r,data_r,ctr_r,data,led);
input rst,pclk,link_i;
input [15:0] addr_arm;
input [15:0] data_arm;
input [2:0] ctr_arm;
inout [15:0] data_l,data_r;
output [15:0] addr_l,addr_r;
output [2:0] ctr_l,ctr_r; //willow change CE OE WR (UB LB)
output link_o;
output [3:0] row;
output lock,ser_clk,en,le,oe,str;
output [15:0] data;
output led;
wire [15:0]count_addr;
wire [2:0] addr_bit;
wire [9:0] addr_colum;
wire [3:0] addr_row;
wire frame,clk;
wire l_r;
signal signal1(rst,clk,pclk,frame,row,link_i,link_o,
ser_clk,lock,str,addr_bit,l_r,addr_colum,
addr_row,count_addr);
wr_rd wr_rd1(addr_arm,data_arm,ctr_arm,addr_l,data_l,
ctr_l,addr_r,data_r,ctr_r,data,l_r,addr_colum,addr_row,count_addr,
oe,le);
machine machine1(clk,str,en,rst,led);
endmodule
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