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发表于 2012-3-29 09:44:41
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终于在昨天搞掂了显示板,并且写了一段代码测试了一下,暂时没有发现问题.
- module lcd( clk,rst_in,
- mcu_cs,mcu_ale,mcu_we,mcu_re,mcu_ad,mcu_addr,mcu_req_we,
- sram_cs,sram_we,sram_re,sram_ub,sram_lb,sram_data,sram_addr,
- rgb_clk,rgb_disp,rgb_den,rgb_light,rgb_hsync,rgb_vsync,rgb_r,rgb_g,rgb_b,
- tp);
-
- input clk,rst_in;
- //mcu interface (25 pins)
- input mcu_cs,mcu_ale,mcu_we,mcu_re;
- input [15:0] mcu_ad;
- input [19:16] mcu_addr;
- output reg mcu_req_we;
- reg [19:0] mcu_reg_addr;
- reg [15:0] mcu_reg_data;
- wire mcu_wereq;
- //sram interface (40 pins)
- output reg sram_cs;
- output sram_ub,sram_lb;
- output reg sram_we,sram_re;
- inout reg [15:0] sram_data;
- output reg [18:0] sram_addr;
- reg mcu_req_complete,rgb_req_complete;
- assign sram_ub=1'b0;
- assign sram_lb=1'b0;
- //rgb interface (30 pins)
- output reg rgb_clk,rgb_hsync,rgb_vsync;
- output rgb_disp,rgb_den;
- output reg rgb_light;
- output reg [7:0] rgb_r,rgb_g,rgb_b;
- reg [15:0] rgb_data;
- reg rgb_req_re;
- reg [17:0] rgb_addr;
- reg [3:0] clkcnt;
- reg [13:0] hcnt;
- reg [21:0] vcnt;
- assign rgb_den=1'b0;
- //assign rgb_light=rst;
- assign rgb_disp=rst;
- //test point interface
- output reg [3:0] tp;
- /********************************************************************
- POWER ON RESET
- ********************************************************************/
- wire rst;
- reg por;
- reg [24:0] porcnt;
- initial begin
- por<=1'b0;
- porcnt<=25'h0;
- end
- always@(posedge clk or negedge rst_in) begin
- if(!rst_in) begin
- por<=1'b0;
- rgb_light<=1'b0;
- porcnt<=25'h0;
- end else begin
- porcnt<=porcnt+1;
- if(porcnt==25'd13300000)
- por<=1'b1;
- if(porcnt==25'd33250000)
- rgb_light<=1'b1;
- end
- end
- assign rst=rst_in & por;
- /********************************************************************
- MCU INTERFACE
- ********************************************************************/
- initial begin
- mcu_req_we<=1'b0;
- mcu_reg_addr<=20'h0;
- end
- assign mcu_wereq=mcu_req_we ^ mcu_req_complete;
- //always@(posedge mcu_ale or negedge rst) begin
- // if(!rst)
- // mcu_reg_addr<=20'hz;
- // else begin
- // if(!mcu_wereq) begin
- // if(!mcu_cs)
- // mcu_reg_addr<={mcu_addr[19:16],mcu_ad[15:0]};
- // end
- // end
- //end
- //
- //always@(posedge mcu_we or negedge rst) begin
- // if(!rst) begin
- // mcu_req_we<=1'b0;
- // mcu_reg_data<=16'hz;
- // end else begin
- // if(!mcu_wereq) begin
- // if(!mcu_cs) begin
- // mcu_reg_data<=mcu_ad;
- // mcu_req_we<=~mcu_req_we;
- // end
- // end
- // end
- //end
- // ******************************************************************
- // MCU Write Test
- // ******************************************************************
- reg [26:0] mcu_div;
- reg [1:0] color;
- initial begin
- mcu_div<=27'h0;
- color<=2'h0;
- end
- always@(posedge clk or negedge rst) begin
- if(!rst) begin
- mcu_div<=18'h0;
- mcu_reg_addr<=20'h0;
- mcu_reg_data<=16'hFFFF;
- mcu_req_we<=1'b0;
- color<=2'h0;
- end else begin
- mcu_div<=mcu_div+1;
- if(mcu_div==18'd8) begin
- mcu_req_we<=~mcu_req_we;
- end else if(mcu_div==18'd1018) begin
- mcu_div<=18'h0;
- mcu_reg_addr<=mcu_reg_addr+1;
- if(mcu_reg_addr==20'd130559) begin //480*272=130560
- mcu_reg_addr<=20'h0;
- color<=color+1;
- case(color)
- 0: mcu_reg_data<=16'hF800;
- 1: mcu_reg_data<=16'h07E0;
- 2: mcu_reg_data<=16'h001F;
- 3: mcu_reg_data<=16'hFFFF;
- endcase
- end
- end
- end
- end
- /********************************************************************
- SRAM INTERFACE
- ********************************************************************/
- reg [2:0] sram_s;
- initial begin
- {mcu_req_complete,rgb_req_complete}<=2'b00;
- {sram_cs,sram_we,sram_re}<=3'b111;
- sram_data<=16'hz;
- sram_addr<=20'hz;
- sram_s<=3'h0;
- end
- //assign sram_cs=~rst;
- always@(posedge clk or negedge rst) begin
- if(!rst) begin
- {mcu_req_complete,rgb_req_complete}<=2'b00;
- {sram_cs,sram_we,sram_re}<=3'b111;
- sram_data<=16'hz;
- sram_addr<=20'hz;
- sram_s<=3'h0;
- end else begin
- if(sram_s==0) begin
- if(rgb_req) begin
- // RGB DATA Read
- sram_s<=3'h1;
- sram_addr<=rgb_addr;
- sram_data<=16'hz;
- {sram_re,sram_cs}<=2'b00;
- end else if(mcu_wereq) begin
- // MCU DATA Write
- sram_s<=3'h4;
- sram_addr<=mcu_reg_addr[18:0];
- sram_data<=mcu_reg_data;
- {sram_we,sram_cs}<=2'b00;
- end
- end else begin
- // sram_s != 0
- sram_s<=sram_s+1;
- case(sram_s)
- 1: rgb_req_complete<=~rgb_req_complete;
- 2: begin
- rgb_data<=sram_data;
- tp<=sram_data[3:0];
- {sram_re,sram_cs}<=2'b11;
- sram_s<=3'h0;
- end
- 4: mcu_req_complete<=~mcu_req_complete;
- // 5: sram_we<=1'b1;
- 5: begin
- sram_data<=16'hz;
- {sram_we,sram_cs}<=2'b11;
- sram_s<=3'h0;
- end
- endcase
- end // end of if(sram_s==0)
- end
- end
- /********************************************************************
- RGB INTERFACE
- [ 523(480+43) * 284(272+12) ]
- ********************************************************************/
- wire rgb_req;
- reg rgb_s;
- initial begin
- rgb_s<=1'b0;
-
- rgb_clk<=1'b0;
- rgb_hsync<=1'b0;
- rgb_vsync<=1'b0;
-
- rgb_data<=16'hx;
- rgb_req_re<=1'b0;
- rgb_addr<=18'h3FFFF;
-
- clkcnt<=4'h0;
- hcnt<=14'h0;
- vcnt<=22'h0;
-
- rgb_r<=8'h0;
- rgb_g<=8'h0;
- rgb_b<=8'h0;
- end
- assign rgb_req=rgb_req_re ^ rgb_req_complete;
- always@(posedge clk or negedge rst) begin
- if(!rst) begin
- clkcnt<=4'h0;
- hcnt<=14'h0;
- vcnt<=22'h0;
- end else begin
- clkcnt<=clkcnt+1;
- hcnt<=hcnt+1;
- vcnt<=vcnt+1;
- if(hcnt==14'd8367) //523*16=8368
- hcnt<=14'h0;
- if(vcnt==22'd2376511) //8368*284=2376512
- vcnt<=22'h0;
- end
- end
- reg [9:0] count;
- //RGB_CLK
- always@(posedge clk or negedge rst) begin
- if(!rst) begin
- rgb_s<=1'b0;
- rgb_clk<=1'b0;
- rgb_addr<=18'h3FFFF;
- count<=10'd0;
- end else begin
- case(clkcnt)
- 0: begin
- rgb_s<=1'b0;
- if(!rgb_vsync) begin
- rgb_addr<=18'h3FFFF;
- end else if(rgb_hsync) begin
- count<=count+1;
- if(count<10'd480) begin
- rgb_s<=1'b1;
- rgb_addr<=rgb_addr+1;
- end
- end else begin
- count<=10'd0;
- end
- end
- 2: begin
- if(rgb_s)
- rgb_req_re<=~rgb_req_re;
- rgb_s<=1'b0;
- end
- 7: rgb_clk<=~rgb_clk;
- 12: {rgb_r[7:3],rgb_g[7:2],rgb_b[7:3]}=rgb_data[15:0];
- 15: begin
- rgb_clk<=~rgb_clk;
- end
- endcase
- end
- end
- //RGB_HSYNC
- always@(posedge clk or negedge rst)begin
- if(!rst) begin
- rgb_hsync<=1'b0;
- end else begin
- if(hcnt<14'd674) //42*16=672 + 2 = 674
- rgb_hsync<=1'b0;
- else
- rgb_hsync<=1'b1;
- end
- end
- //RGB_VSYNC
- always@(posedge clk or negedge rst)begin
- if(!rst) begin
- rgb_vsync<=1'b0;
- end else begin
- if(vcnt<22'd100418) //8368*12=100416 + 2 = 100418
- rgb_vsync<=1'b0;
- else
- rgb_vsync<=1'b1;
- end
- end
- endmodule
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