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楼主 |
发表于 2012-1-14 12:50:51
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二位比较器的verilog源代码
module comp2bit (
input wire [1:0] a,
input wire [1:0] b,
output wire a_eq_b,
output wire a_gt_b,
output wire a_lt_b
);
assign a_eq_b = ~b[1] & ~b[0] & ~a[1] & ~a[0]
| ~b[1] & b[0] & ~a[1] & a[0]
| b[1] & ~b[0] & a[1] & ~a[0]
| b[1] & b[0] & a[1] & a[0];
assign a_gt_b = ~b[1] & a[1]
| ~b[1] & ~b[0] & a[0]
| ~b[0] & a[1] & a[0];
assign a_lt_b = b[1] & ~a[1]
| b[1] & b[0] & ~a[0]
| b[0] & ~a[1] & ~a[0];
endmodule
二位比较器的VHDL源代码
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comp2bit is
PORT(a: IN STD_LOGIC_vector(1 DOWNTO 0);
b: IN STD_LOGIC_vector(1 DOWNTO 0);
a_eq_b: OUT STD_LOGIC;
a_gt_b: OUT STD_LOGIC;
a_lt_b: OUT STD_LOGIC);
end comp2bit;
architecture Behavioral of comp2bit is
begin
a_eq_b<= (NOT b(1) AND NOT b(0) AND NOT a(1) AND NOT a(0)) OR (NOT b(1) AND b(0) AND NOT a(1) AND a(0))OR (b(1) AND NOT b(0) AND a(1) AND NOT a(0))OR (b(1) AND b(0) AND a(1) AND a(0));
a_gt_b<= (NOT b(1) AND a(1)) OR (NOT b(1) AND NOT b(0) AND a(0)) OR (b(1) AND NOT b(0) AND a(1) AND NOT a(0)) OR (NOT b(1) AND a(1) AND a(0));
a_lt_b<= (b(1) AND NOT a(1)) OR (b(1) AND b(0) AND NOT a(0)) OR (b(1) AND NOT b(0) AND a(1) AND NOT a(0)) OR (b(0) AND NOT a(1) AND NOT a(0));
end Behavioral; |
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