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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity My_All is
port(
my_and_a,
my_and_b
:in bit;
my_and_y
:out bit;
my_adder_a,
my_adder_b
:in STD_LOGIC_VECTOR(2 downto 0);
my_adder_s
:out STD_LOGIC_VECTOR(3 downto 0)
);
end entity My_All;
architecture main of My_All is
begin
my_and:
block
begin
my_and_y <= my_and_a and my_and_b;
end block my_and;
my_adder:
process (my_adder_a,my_adder_b)
function my_adder_unit (add_in:STD_LOGIC_VECTOR(1 downto 0)) return STD_LOGIC_VECTOR(1 downto 0) is
variable tmp:STD_LOGIC_VECTOR( 1 downto 0 );
begin
tmp(0):=add_in(0) xor add_in(1);
tmp(1):=add_in(0) and add_in(1);
return tmp;
end function my_adder_unit;
variable tmp1:bit;
begin
end process my_adder;
end architecture main;
Error (10479): VHDL error at My_All.vhd(31): indexed name type is used but not declared
在网上找到的答案是将return STD_LOGIC_VECTOR(1 downto 0)中的(1 downto 0)去掉。
为什么返回值的长度不严格要求呢? |
阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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