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【八位数码管动态扫描程序】Quartus II 提示的这些警告代表什么?实际下载到芯片中运行正常
程序如下:
CLK是输入时钟,50Mhz,sel是数码管位选择 data是数码管数据 程序在1-8位分别显示数字1-8 数码管扫描频率1khz
//_______________________________________________________
module led8(clk,sel,data);
input clk;
output[7:0] sel;
output[7:0] data;
reg[16:0] clk_count;
reg clk_1khz;
always @(posedge clk)//分频 1khz
begin
if(clk_count==50000)
begin clk_count<=0;clk_1khz<=1;end
else
begin clk_count<=clk_count+1;clk_1khz<=0;end
end
reg[3:0] i;
reg[7:0] sel=8'b01111111;
reg[7:0] data=8'hff;
always @(posedge clk_1khz)//数码管动态扫描
begin
begin
sel<={sel[6:0],sel[7]};
case(i)
3'd0:data<=8'hF9; //"1"
3'd1:data<=8'ha4; //2
3'd2:data<=8'hb0; //3
3'd3:data<=8'h99; //4
3'd4:data<=8'h92; //5
3'd5:data<=8'h82; //6
3'd6:data<=8'hf8; //7
3'd7:data<=8'h80; //8
endcase
end
if(i==7)i<=0;else i<=i+1;
end
endmodule
程序下载后运行正常,但不理解下边这几个错误是何意?还请大家指点……(共6个警告信息)
Warning (10230): Verilog HDL assignment warning at led8.v(13): truncated value with size 32 to match size of target (17)
Warning (10230): Verilog HDL assignment warning at led8.v(34): truncated value with size 32 to match size of target (4)
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "data[7]" is stuck at VCC
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin data[7] has VCC driving its datain port
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_1khz" as buffer
http://www.ourdev.cn/bbs/bbs_content.jsp?bbs_sn=5034538&bbs_id=9999 另此贴也有些疑问,还请大家也指点一二,谢谢了 |
阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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