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写了接和发的程序,verilog描述
115200bps,串口助手100mS发一个字节,FPGA收到后返回原字节,FPGA晶振50MHz
串口助手共发送298个,只收到275个
丢了23,7.x%了
点击此处下载 ourdev_667582P45W1E.rar(文件大小:766字节) (原文件名:USART_RX.rar)
点击此处下载 ourdev_667583U5QS3E.rar(文件大小:1K) (原文件名:USART_TX.rar)
贴个接收的,短些
-----------------------------------------------------
`define UD #1
module USART_RX
(
// input ports
SYSCLK,
RST_B,
RX_IN,
// output ports
RX_FINISH,
RX_DATA
);
//===========================================================================
// Input and output declaration
//===========================================================================
input SYSCLK;
input RST_B;
input RX_IN;
output RX_FINISH;
output [7:0] RX_DATA;
//===========================================================================
// Wire and reg declaration
//===========================================================================
wire SYSCLK;
wire RST_B;
wire RX_IN;
wire RX_FINISH;
reg [7:0] RX_DATA;
//===========================================================================
// Wire and reg in the module
//===========================================================================
reg RX_IN_REG;
reg RX_IN_REG_N;
wire RX_START; // 开始接收
reg [15:0] CLK_DIV_CNT;
reg [15:0] CLK_DIV_CNT_N;
reg [7:0] RX_DATA_N;
//===========================================================================
// Logic
//===========================================================================
always @ (posedge SYSCLK)
RX_IN_REG_N <= `UD RX_IN;
always @ (posedge SYSCLK)
RX_IN_REG <= `UD RX_IN_REG_N;
assign RX_START = (!RX_IN && (RX_IN_REG_N || RX_IN_REG)) ? 1'b1 : 1'b0;
assign RX_FINISH = (CLK_DIV_CNT == 16'h11A3) ? 1'b1 : 1'b0;
// 波特率需要的时钟
always @ (posedge SYSCLK or negedge RST_B)
begin
if(!RST_B)
CLK_DIV_CNT <= `UD 16'h0;
else
CLK_DIV_CNT <= `UD CLK_DIV_CNT_N;
end
always @ (*)
begin
if(RX_START && (CLK_DIV_CNT == 16'h0))
CLK_DIV_CNT_N = 16'h1;
else if(CLK_DIV_CNT == 16'h11A3)
CLK_DIV_CNT_N = 16'h0;
else if(CLK_DIV_CNT != 16'h0)
CLK_DIV_CNT_N = CLK_DIV_CNT + 1'h1;
else
CLK_DIV_CNT_N = CLK_DIV_CNT;
end
//---------------------------------------------------
// 接收数据
always @ (posedge SYSCLK or negedge RST_B)
begin
if(!RST_B)
RX_DATA <= `UD 8'h0;
else
RX_DATA <= `UD RX_DATA_N;
end
always @ (*)
begin
if((CLK_DIV_CNT == 16'h2D0)
|| (CLK_DIV_CNT == 16'h47E)
|| (CLK_DIV_CNT == 16'h62C)
|| (CLK_DIV_CNT == 16'h7DA)
|| (CLK_DIV_CNT == 16'h988)
|| (CLK_DIV_CNT == 16'hB36)
|| (CLK_DIV_CNT == 16'hCE4)
|| (CLK_DIV_CNT == 16'hE92))
RX_DATA_N = {RX_IN, RX_DATA[7:1]};
else
RX_DATA_N = RX_DATA;
end
endmodule |
阿莫论坛20周年了!感谢大家的支持与爱护!!
曾经有一段真挚的爱情摆在我的面前,我没有珍惜,现在想起来,还好我没有珍惜……
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