VHDL小源码(无需回复，自己持续更新）

40130064 · 发表于 2011-7-30 09:43:51

一.积分分频（小数分频）注：只是对平均频率，输出不均匀。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY FDIV IS
PORT (
   clkin                   : in std_logic;
   clkout       :out std_logic);
END FDIV;

ARCHITECTURE epm570 OF FDIV IS
SIGNAL delay          :  std_logic;
   SIGNAL q          :  std_logic_vector(3 downto 0);

BEGIN
PROCESS
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
delay <=q(3);
q <= q+6;
END PROCESS;

clkout <=(q(3) xor delay) and not clkin;
END epm570;

40130064 · 发表于 2011-7-30 09:46:20

二.上升沿，下降沿微分电路。
clk    :时钟大于大于din
din    :输入信号
up_diff ：din 上升沿后输出一个clk周期宽的脉冲
dn_diff ：din 下降沿后输出一个clk周期宽的脉冲

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY DIFF IS
PORT (
   clk                   : in std_logic;
   din                      : in std_logic;
   up_diff,dn_diff       :out std_logic);
END DIFF;

ARCHITECTURE epm570 OF DIFF IS
SIGNAL t1,t2             :  std_logic;

BEGIN
PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1');
t2 <= t1;
t1 <= din;
END PROCESS;

up_diff<=t1 AND NOT t2;
dn_diff<=NOT t1 AND t2;

END epm570;

yuphone · 发表于 2011-7-30 10:40:52

留爪

hubeilcsun3 · 发表于 2011-7-30 11:22:48

果断mark

jlhgold · 发表于 2011-7-30 11:58:03

mark

40130064 · 发表于 2011-7-30 14:27:52

三.下降沿单稳态电路，或类似定时器之类。
clk：时钟
tclk：  触发输入
delayout ：输出脉宽=delaymax*clk周期

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY DELAY_T IS
GENERIC (delaymax:integer:=4);
PORT (
   clk                   : in std_logic;
   tclk    : in std_logic;
   delayout    :buffer std_logic);
END DELAY_T;

ARCHITECTURE epm570 OF DELAY_T IS
SIGNAL tclk_1          :  std_logic;

BEGIN
PROCESS(tclk,tclk_1)
BEGIN
if (tclk_1='1')then
delayout<='0';
elsif(tclk'EVENT AND tclk = '0')then
delayout<='1';
end if;
END PROCESS;

PROCESS(clk,delayout)
variable delayT: integer range 0 to delaymax:=0;
BEGIN
if (delayout='0')then
delayT:=0;
tclk_1<='0';
else if(clk'EVENT AND clk = '1')then
if(delayT=delaymax)then
tclk_1<='1';
end if;
delayT:=delayT+1;
end if;
end if;
END PROCESS;

END epm570;

Tomas_Yung · 发表于 2011-7-30 16:06:05

不错！

jjjcmxz · 发表于 2011-7-30 16:31:02

mark 下

amote · 发表于 2011-7-30 16:31:43

mark

qdhd_hai · 发表于 2011-7-30 16:44:30

mark

fanspring · 发表于 2011-8-5 00:43:12

初学者路过

40130064 · 发表于 2011-8-17 13:48:31

梯形加减脉冲产生程序，只提供方法，可简单应用。
   load    加载参数，高电平
   pulout    输出
   puldata    产生脉冲的总数
   smax       工作速度 1-250
   smin       起始速度 1-250
   lnub       到达最低速度后输出的脉冲个数

(原文件名:未命名.jpg)



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY TPJ IS
GENERIC (lnub:integer:=0);

PORT (
   clk                   : IN std_logic;
   load                   : IN std_logic;
   en                   : IN std_logic;
   pulout                : out std_logic;
   puldata                : in  std_logic_vector(15 DOWNTO 0);
   smax                   : in  std_logic_vector(7 DOWNTO 0);
   smin                   : in  std_logic_vector(7 DOWNTO 0));
END TPJ;

ARCHITECTURE epm570 OF TPJ IS
SIGNAL smax_0 :  std_logic_vector(7 DOWNTO 0);
SIGNAL sq_r :  std_logic_vector(7 DOWNTO 0);
SIGNAL smin_r  :  std_logic_vector(7 DOWNTO 0);
SIGNAL dir_r : std_logic;
SIGNAL puldata_r : std_logic_vector(15 DOWNTO 0);

BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk = '1')THEN
if ((puldata-puldata_r)<smin+lnub) then

dir_r<='0';
else
dir_r<='1';
end if;
end if;
END PROCESS;

PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk = '1')THEN
if (load='1')then
sq_r <="00000000" ;
smin_r <=smin ;
smax_0 <=smin ;
end if;
if (en='1')then

if(puldata_r=puldata)then
pulout<='0';
else

if(dir_r='1')then
if (sq_r<smin_r)then
sq_r <= sq_r + 1;
pulout<='1';
else
sq_r<="00000000";
if (smin_r>smax)then
smin_r<=smin_r-1;
else
smin_r<=smax;
end if;
pulout<='0';
puldata_r<=puldata_r+'1';
END IF;
else
if (sq_r<(smin_r))then
sq_r <= sq_r + 1;
pulout<='1';
else
sq_r<="00000000";
if (smin_r<smax_0)then
smin_r<=smin_r+1;
else
smin_r<=smax_0;
end if;
pulout<='0';
puldata_r<=puldata_r+'1';
END IF;
   end if;

      end if;
end if;
end if;
END PROCESS;
END epm570;

xibu1102007 · 发表于 2011-8-26 18:30:57

多谢啊

EEer08 · 发表于 2011-8-26 20:35:30

mark

yishangyi · 发表于 2011-8-26 21:17:18

mark

chahu1227 · 发表于 2011-9-8 12:21:15

mark

ledatou · 发表于 2011-9-11 17:56:51

果断mark先！！！

tianpengyu · 发表于 2011-9-24 21:43:20

还是VHDL 看着亲切些......

jobs_start · 发表于 2011-10-7 23:55:04

VHDL小源码(无需回复，自己持续更新）

阿莫论坛20周年了！感谢大家的支持与爱护！！