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楼主 |
发表于 2011-7-17 14:44:21
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//water led
module water_led(clk,rst_n,led_out);
input clk;//clock
input rst_n;
output [3:0] led_out;//water led output
reg [3:0] led_tag = 1'b1;//status tag
reg [2:0] counter = 1'b0;//counter
//division clock
always @(posedge clk)
begin
if(!rst_n) begin
counter <= 0;
led_tag <= 1'b1;
end
else
counter <= counter + 1'b1;
if(counter == 3'd5/*0_000_000*/) begin
led_tag[3:0] = led_tag[3:0]<<1'b1;
if(led_tag[3:0] == 1'b0)
led_tag[3:0] <= 1'b1;
counter <= 1'b0;
end
end
//assignment voluation
assign led_out[3:0] = led_tag[3:0];
endmodule
这段小程序改改后,编译不过去
//water led
module water_led(clk,rst_n,led_out);
input clk;//clock
input rst_n;
output [3:0] led_out;//water led output
reg [3:0] led_tag = 1'b1;//status tag
reg [2:0] counter = 1'b0;//counter
//division clock
always @(posedge clk,negedge rst_n)
begin
if(!rst_n) begin
counter <= 0;
led_tag <= 1'b1;
end
else
counter <= counter + 1'b1;
if(counter == 3'd5/*0_000_000*/) begin
led_tag[3:0] = led_tag[3:0]<<1'b1;
if(led_tag[3:0] == 1'b0)
led_tag[3:0] <= 1'b1;
counter <= 1'b0;
end
end
//assignment voluation
assign led_out[3:0] = led_tag[3:0];
endmodule
提示:
Error (10200): Verilog HDL Conditional Statement error at water_led.v(17): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
为啥子呢? |
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