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程序下载后总是一开始是好使的，但是运行一段时间后，发现输入信号有，但是输出信号就没有了。用SIGNAL TAP调试，发现程序 又很好使，问题始终不出现。但是去掉下载到FPGA中，一段时间后又死机了。无奈先不开启SIGNAL TAP，等到死机出现后再开捕捉，发现状态机的所有状态都是低，状态机死掉了。程序如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cyc_rdram is
PORT(
reset:in STD_LOGIC;
rdram_clk:in STD_LOGIC;--5MHZ
mcu_wr_ready:in STD_LOGIC;
rd_addr:out STD_LOGIC_VECTOR(7 DOWNTO 0);
rd_data:in STD_LOGIC_VECTOR(7 DOWNTO 0);
ram_rd:out STD_LOGIC;
clk_jk:out STD_LOGIC;
FPGA_clk_en_rd:out STD_LOGIC;
spi_en:out STD_LOGIC;
spi_data:out STD_LOGIC_VECTOR(15 DOWNTO 0);
dsyn:out STD_LOGIC_VECTOR(15 DOWNTO 0);
jsyn:out STD_LOGIC_VECTOR(15 DOWNTO 0);
syn_en:out STD_LOGIC;
pwm_on:out STD_LOGIC_VECTOR(23 DOWNTO 0);
pwm_off:out STD_LOGIC_VECTOR(23 DOWNTO 0);
pwm_en:out STD_LOGIC
);
end cyc_rdram;
architecture dev of cyc_rdram is
constant spi_addr1:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000010";
constant spi_addr2:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000011";
constant dsyn_addr1:STD_LOGIC_VECTOR(7 DOWNTO 0):="00001010";
constant dsyn_addr2:STD_LOGIC_VECTOR(7 DOWNTO 0):="00001011";
constant jsyn_addr1:STD_LOGIC_VECTOR(7 DOWNTO 0):="00001100";
constant jsyn_addr2:STD_LOGIC_VECTOR(7 DOWNTO 0):="00001101";
constant pwm_on_addr1:STD_LOGIC_VECTOR(7 DOWNTO 0):="00001110";
constant pwm_on_addr2:STD_LOGIC_VECTOR(7 DOWNTO 0):="00001111";
constant pwm_on_addr3:STD_LOGIC_VECTOR(7 DOWNTO 0):="00010000";
constant pwm_off_addr1:STD_LOGIC_VECTOR(7 DOWNTO 0):="00010001";
constant pwm_off_addr2:STD_LOGIC_VECTOR(7 DOWNTO 0):="00010010";
constant pwm_off_addr3:STD_LOGIC_VECTOR(7 DOWNTO 0):="00010011";
type states is(idle,st0,st1,st2,st3,st4);
signal state_c:states;
signal num:integer range 0 to 15;
begin
process(rdram_clk,reset)
begin
if(reset='0')then
state_c<=idle;
ram_rd<='0';
clk_jk<='0';
FPGA_clk_en_rd<='0';
spi_en<='0';
syn_en<='0';
pwm_en<='0';
num<=0;
elsif(rising_edge(rdram_clk))then
case state_c is
when idle =>
ram_rd<='0';
clk_jk<='0';
spi_en<='0';
syn_en<='0';
pwm_en<='0';
FPGA_clk_en_rd<='0';
num<=0;
if(mcu_wr_ready='1')then
state_c<=st0;
else
state_c<=idle;
end if;
when st0 =>
ram_rd<='0';
clk_jk<='0';
spi_en<='0';
syn_en<='0';
pwm_en<='0';
FPGA_clk_en_rd<='0';
if(mcu_wr_ready='0')then
state_c<=st1;
else
state_c<=st0;
end if;
when st1 =>
if(num=0)then
rd_addr<=spi_addr1;
elsif(num=1)then
rd_addr<=spi_addr2;
elsif(num=2)then
rd_addr<=dsyn_addr1;
elsif(num=3)then
rd_addr<=dsyn_addr2;
elsif(num=4)then
rd_addr<=jsyn_addr1;
elsif(num=5)then
rd_addr<=jsyn_addr2;
elsif(num=6)then
rd_addr<=pwm_on_addr1;
elsif(num=7)then
rd_addr<=pwm_on_addr2;
elsif(num=8)then
rd_addr<=pwm_on_addr3;
elsif(num=9)then
rd_addr<=pwm_off_addr1;
elsif(num=10)then
rd_addr<=pwm_off_addr2;
elsif(num=11)then
rd_addr<=pwm_off_addr3;
else
num<=11;
end if;
ram_rd<='1';
clk_jk<='0';
FPGA_clk_en_rd<='0';
state_c<=st2;
when st2 =>
ram_rd<='1';
clk_jk<='1';
FPGA_clk_en_rd<='1';
state_c<=st3;
when st3 =>
ram_rd<='0';
clk_jk<='0';
if(num=0)then
FPGA_clk_en_rd<='1';
spi_en<='1';
spi_data(15 DOWNTO 8)<=rd_data;
state_c<=st1;
elsif(num=1)then
spi_en<='1';
FPGA_clk_en_rd<='1';
spi_data(7 DOWNTO 0)<=rd_data;
state_c<=st1;
elsif(num=2)then
FPGA_clk_en_rd<='1';
spi_en<='1';
syn_en<='1';
dsyn(15 DOWNTO 8)<=rd_data;
state_c<=st1;
elsif(num=3)then
FPGA_clk_en_rd<='1';
spi_en<='1';
syn_en<='1';
dsyn(7 DOWNTO 0)<=rd_data;
state_c<=st1;
elsif(num=4)then
FPGA_clk_en_rd<='1';
spi_en<='1';
syn_en<='1';
jsyn(15 DOWNTO 8)<=rd_data;
state_c<=st1;
elsif(num=5)then
FPGA_clk_en_rd<='1';
spi_en<='0';
syn_en<='0';
jsyn(7 DOWNTO 0)<=rd_data;
state_c<=st1;
elsif(num=6)then
FPGA_clk_en_rd<='1';
pwm_en<='1';
pwm_on(23 DOWNTO 16)<=rd_data;
state_c<=st1;
elsif(num=7)then
FPGA_clk_en_rd<='1';
pwm_en<='1';
pwm_on(15 DOWNTO 8)<=rd_data;
state_c<=st1;
elsif(num=8)then
FPGA_clk_en_rd<='1';
pwm_en<='1';
pwm_on(7 DOWNTO 0)<=rd_data;
state_c<=st1;
elsif(num=9)then
FPGA_clk_en_rd<='1';
pwm_en<='1';
pwm_off(23 DOWNTO 16)<=rd_data;
state_c<=st1;
elsif(num=10)then
FPGA_clk_en_rd<='1';
pwm_en<='1';
pwm_off(15 DOWNTO 8)<=rd_data;
state_c<=st1;
elsif(num=11)then
FPGA_clk_en_rd<='1';
pwm_en<='0';
pwm_off(7 DOWNTO 0)<=rd_data;
state_c<=st4;
else
state_c<=st4;
end if;
num<=num+1;
when st4 =>
num<=0;
ram_rd<='0';
clk_jk<='0';
FPGA_clk_en_rd<='0';
spi_en<='0';
syn_en<='0';
pwm_en<='0';
state_c<=idle;
when OTHERS => state_c<=idle;
end case;
end if;
end process;
end dev;
各位大虾，可否给支个招？在下感激不尽。 |
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知道什么是神吗？其实神本来也是人，只不过神做了人做不到的事情 所以才成了神。 （头文字D, 杜汶泽）
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发表于 2011-5-31 15:24:22
停止在IDLE，应该考察下从IDLE出来的条件，看看mcu_wr_ready这个外部信号线是否总是为低(原文件名:FSM.JPG)
楼主