哪位高手看下，我这段VHDL程序哪里出错了，查不来

whj19860123 · 发表于 2011-3-9 09:27:52

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder is
port
(
   clk  : in std_logic;
      a : in  std_logic_vector (7 DOWNTO 0 );
            c  : out std_logic_vector (7 DOWNTO 0 )
);
end entity;
architecture rtl of adder is
signal c_tmp :  std_logic_vector (7 downto 0);
begin
c<=c_tmp;
process (clk)
begin
      if(a(7)='1') then c_tmp<="1000";
   elsif(a(6)='1') then c_tmp<="0111";
   elsif(a(5)='1') then c_tmp<="0110";
   elsif(a(4)='1') then c_tmp<="0101";
   elsif(a(3)='1') then c_tmp<="0100";
   elsif(a(2)='1') then c_tmp<="0011";
   elsif(a(1)='1') then c_tmp<="0010";
   elsif(a(0)='1') then c_tmp<="0001";
   else c_tmp<="0000";
   end if;
end process;
end rtl;

whj19860123 · 发表于 2011-3-9 09:31:24

这个是8位优先编码器，就是编译不能通过

whj19860123 · 发表于 2011-3-9 09:33:41

Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 8 warnings
Error: Peak virtual memory: 185 megabytes
Error: Processing ended: Wed Mar 09 09:27:09 2011
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 8 warnings

whj19860123 · 发表于 2011-3-9 09:48:02

自己查到问题了，c : out std_logic_vector (7 DOWNTO 0 ) signal c_tmp : std_logic_vector (7 downto 0);
改成4位就可以了呵呵

whj19860123 · 发表于 2011-3-9 10:05:59

还有波形仿真时候：不把 process (clk) 改成 process (clk，a) 就仿真不出来？？？？？？？

highyo88 · 发表于 2011-3-10 21:17:54

呵呵，楼主自个就解决了，我也是最近开始学FPGA的，一起努力

哪位高手看下，我这段VHDL程序哪里出错了，查不来

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