|
subtype ROM_WORD is std_logic_vector (31 downto 0);
type ROM_TABLE is array (0 to 15) of ROM_WORD;
constant Zero_32 :ROM_WORD := "00000000000000000000000000000000";
constant RomWord13 :ROM_WORD := "000000000000000000000000"& CAP_PTR;
constant RomWord15 :ROM_WORD := MAX_LAT & MIN_GNT & INT_PIN &INT_LINE;
constant ROM: ROM_TABLE := ROM_TABLE'(
ROM_WORD'(DEVICE_ID & VENDOR_ID),
ROM_WORD'(Zero_32),
ROM_WORD'(CLASS_ID & REV_ID),
ROM_WORD'(Zero_32),
ROM_WORD'(BAR0_MAP),
ROM_WORD'(BAR1_MAP),
ROM_WORD'(BAR2_MAP),
ROM_WORD'(BAR3_MAP),
ROM_WORD'(BAR4_MAP),
ROM_WORD'(BAR5_MAP),
ROM_WORD'(Zero_32),
ROM_WORD'(SUBDEVICE_ID & SUBVENDOR_ID,
ROM_WORD'(EBAR_MAP),
ROM_WORD'(RomWord13),
ROM_WORD'(Zero_32),
ROM_WORD'(MAX_LAT & MIN_GNT & INT_PIN &INT_LINE));
以上是VHDL写的,verilog中怎么写?? |
阿莫论坛20周年了!感谢大家的支持与爱护!!
知道什么是神吗?其实神本来也是人,只不过神做了人做不到的事情 所以才成了神。 (头文字D, 杜汶泽)
|