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发表于 2011-2-7 13:44:01
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回复【1楼】kerenyang
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以下是testbench,请教高人解答,不胜感激
`timescale 1ps/1ps
module ex3_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg rst_n;
// wires
wire fm;
// assign statements (if any)
ex3 i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.fm(fm),
.rst_n(rst_n)
);
initial begin
clk=0;
forever
#10 clk=~clk;
end
initial begin
rst_n=0;
#1000;
rst_n=1;
#5000;
$stop;
end
endmodule |
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