|
装了个modelsimSE 6.6C 为什么在quartus里面调用它,它多要编译一大推的库文件。
原来是用6.5的,后来改成而来6.6,6.6 好像很慢,启动卡。
原来6.5好快,也不用编译一大堆的库,why?
# Reading D:/modelsimse_6.6c/tcl/vsim/pref.tcl
# // ModelSim SE 6.6c Aug 23 2010
# //
# // Copyright 1991-2010 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do SRAM_Demo_run_msim_rtl_verilog.do
# if ![file isdirectory verilog_libs] {
# file mkdir verilog_libs
# }
#
# vlib verilog_libs/altera_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_ver".
# vmap altera_ver ./verilog_libs/altera_ver
# Copying D:\modelsimse_6.6c\win32/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\modelsimse_6.6c\win32/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
# vlog -vlog01compat -work altera_ver {d:/altera/10.1/quartus/eda/sim_lib/altera_primitives.v}
# Model Technology ModelSim SE vlog 6.6c Compiler 2010.08 Aug 23 2010
# -- Compiling module global
# -- Compiling module carry
# -- Compiling module cascade
# -- Compiling module carry_sum
# -- Compiling module exp
# -- Compiling module soft
# -- Compiling module opndrn
# -- Compiling module row_global
# -- Compiling module TRI
# -- Compiling module lut_input
# -- Compiling module lut_output
# -- Compiling module latch
# -- Compiling module dlatch
# -- Compiling module prim_gdff
# -- Compiling module dff
# -- Compiling module dffe
# -- Compiling module dffea
# -- Compiling module dffeas
# -- Compiling module prim_gtff
# -- Compiling module tff
# -- Compiling module tffe
# -- Compiling module prim_gjkff
# -- Compiling module jkff
# -- Compiling module jkffe
# -- Compiling module prim_gsrff
# -- Compiling module srff
# -- Compiling module srffe
# -- Compiling module clklock
# -- Compiling module alt_inbuf
# -- Compiling module alt_outbuf
# -- Compiling module alt_outbuf_tri
# -- Compiling module alt_iobuf
# -- Compiling module alt_inbuf_diff
# -- Compiling module alt_outbuf_diff
# -- Compiling module alt_outbuf_tri_diff
# -- Compiling module alt_iobuf_diff
# -- Compiling module alt_bidir_diff
# -- Compiling module alt_bidir_buf
# -- Compiling UDP PRIM_GDFF_LOW
# -- Compiling UDP PRIM_GDFF_HIGH
#
# Top level modules:
# global
# carry
# cascade
# carry_sum
# exp
# soft
# opndrn
# row_global
# TRI
# lut_input
# lut_output
# latch
# dlatch
# dff
# dffe
# dffea
# dffeas
# tff
# tffe
# jkff
# jkffe
# srff
# srffe
# clklock
# alt_inbuf
# alt_outbuf
# alt_outbuf_tri
# alt_iobuf
# alt_inbuf_diff
# alt_outbuf_diff
# alt_outbuf_tri_diff
# alt_iobuf_diff
# alt_bidir_diff
# alt_bidir_buf
#
# vlib verilog_libs/lpm_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/lpm_ver".
# vmap lpm_ver ./verilog_libs/lpm_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work lpm_ver {d:/altera/10.1/quartus/eda/sim_lib/220model.v}
# Model Technology ModelSim SE vlog 6.6c Compiler 2010.08 Aug 23 2010
# -- Compiling module LPM_MEMORY_INITIALIZATION
# -- Compiling module LPM_HINT_EVALUATION
# -- Compiling module LPM_DEVICE_FAMILIES
# -- Compiling module lpm_constant
# -- Compiling module lpm_inv
# -- Compiling module lpm_and
# -- Compiling module lpm_or
# -- Compiling module lpm_xor
# -- Compiling module lpm_bustri
# -- Compiling module lpm_mux
# -- Compiling module lpm_decode
# -- Compiling module lpm_clshift
# -- Compiling module lpm_add_sub
# -- Compiling module lpm_compare
# -- Compiling module lpm_mult
# -- Compiling module lpm_divide
# -- Compiling module lpm_abs
# -- Compiling module lpm_counter
# -- Compiling module lpm_latch
# -- Compiling module lpm_ff
# -- Compiling module lpm_shiftreg
# -- Compiling module lpm_ram_dq
# -- Compiling module lpm_ram_dp
# -- Compiling module lpm_ram_io
# -- Compiling module lpm_rom
# -- Compiling module lpm_fifo
# -- Compiling module lpm_fifo_dc_dffpipe
# -- Compiling module lpm_fifo_dc_fefifo
# -- Compiling module lpm_fifo_dc_async
# -- Compiling module lpm_fifo_dc
# -- Compiling module lpm_inpad
# -- Compiling module lpm_outpad
# -- Compiling module lpm_bipad
#
# Top level modules:
# lpm_constant
# lpm_inv
# lpm_and
# lpm_or
# lpm_xor
# lpm_bustri
# lpm_mux
# lpm_decode
# lpm_clshift
# lpm_add_sub
# lpm_compare
# lpm_mult
# lpm_divide
# lpm_abs
# lpm_counter
# lpm_latch
# lpm_ff
# lpm_shiftreg
# lpm_ram_dq
# lpm_ram_dp
# lpm_ram_io
# lpm_rom
# lpm_fifo
# lpm_fifo_dc
# lpm_inpad
# lpm_outpad
# lpm_bipad
#
# vlib verilog_libs/sgate_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/sgate_ver".
# vmap sgate_ver ./verilog_libs/sgate_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work sgate_ver {d:/altera/10.1/quartus/eda/sim_lib/sgate.v}
# Model Technology ModelSim SE vlog 6.6c Compiler 2010.08 Aug 23 2010
# -- Compiling module oper_add
# -- Compiling module oper_addsub
# -- Compiling module mux21
# -- Compiling module io_buf_tri
# -- Compiling module io_buf_opdrn
# -- Compiling module oper_mult
# -- Compiling module tri_bus
# -- Compiling module oper_div
# -- Compiling module oper_mod
# -- Compiling module oper_left_shift
# -- Compiling module oper_right_shift
# -- Compiling module oper_rotate_left
# -- Compiling module oper_rotate_right
# -- Compiling module oper_less_than
# -- Compiling module oper_mux
# -- Compiling module oper_selector
# -- Compiling module oper_decoder
# -- Compiling module oper_bus_mux
# -- Compiling module oper_latch
#
# Top level modules:
# oper_add
# oper_addsub
# mux21
# io_buf_tri
# io_buf_opdrn
# oper_mult
# tri_bus
# oper_div
# oper_mod
# oper_left_shift
# oper_right_shift
# oper_rotate_left
# oper_rotate_right
# oper_less_than
# oper_mux
# oper_selector
# oper_decoder
# oper_bus_mux
# oper_latch
#
# vlib verilog_libs/altera_mf_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_mf_ver".
# vmap altera_mf_ver ./verilog_libs/altera_mf_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work altera_mf_ver {d:/altera/10.1/quartus/eda/sim_lib/altera_mf.v}
# Model Technology ModelSim SE vlog 6.6c Compiler 2010.08 Aug 23 2010
# -- Compiling module lcell
# -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
# -- Compiling module ALTERA_MF_HINT_EVALUATION
# -- Compiling module ALTERA_DEVICE_FAMILIES
# -- Compiling module dffp
# -- Compiling module pll_iobuf
# -- Compiling module stx_m_cntr
# -- Compiling module stx_n_cntr
# -- Compiling module stx_scale_cntr
# -- Compiling module MF_pll_reg
# -- Compiling module MF_stratix_pll
# -- Compiling module arm_m_cntr
# -- Compiling module arm_n_cntr
# -- Compiling module arm_scale_cntr
# -- Compiling module MF_stratixii_pll
# -- Compiling module ttn_m_cntr
# -- Compiling module ttn_n_cntr
# -- Compiling module ttn_scale_cntr
# -- Compiling module MF_stratixiii_pll
# -- Compiling module cda_m_cntr
# -- Compiling module cda_n_cntr
# -- Compiling module cda_scale_cntr
# -- Compiling module MF_cycloneiii_pll
# -- Compiling module MF_cycloneiiigl_m_cntr
# -- Compiling module MF_cycloneiiigl_n_cntr
# -- Compiling module MF_cycloneiiigl_scale_cntr
# -- Compiling module cycloneiiigl_post_divider
# -- Compiling module MF_cycloneiiigl_pll
# -- Compiling module altpll
# -- Compiling module altlvds_rx
# -- Compiling module stratix_lvds_rx
# -- Compiling module stratixgx_dpa_lvds_rx
# -- Compiling module stratixii_lvds_rx
# -- Compiling module flexible_lvds_rx
# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel
# -- Compiling module stratixiii_lvds_rx_dpa
# -- Compiling module altlvds_tx
# -- Compiling module stratix_tx_outclk
# -- Compiling module stratixii_tx_outclk
# -- Compiling module flexible_lvds_tx
# -- Compiling module dcfifo_dffpipe
# -- Compiling module dcfifo_fefifo
# -- Compiling module dcfifo_async
# -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency
# -- Compiling module dcfifo_mixed_widths
# -- Compiling module dcfifo
# -- Compiling module altaccumulate
# -- Compiling module altmult_accum
# -- Compiling module altmult_add
# -- Compiling module altfp_mult
# -- Compiling module altsqrt
# -- Compiling module altclklock
# -- Compiling module altddio_in
# -- Compiling module altddio_out
# -- Compiling module altddio_bidir
# -- Compiling module altdpram
# -- Compiling module altsyncram
# -- Compiling module alt3pram
# -- Compiling module parallel_add
# -- Compiling module scfifo
# -- Compiling module altshift_taps
# -- Compiling module a_graycounter
# -- Compiling module altsquare
# -- Compiling module altera_std_synchronizer
# -- Compiling module altera_std_synchronizer_bundle
# -- Compiling module alt_cal
# -- Compiling module alt_cal_mm
# -- Compiling module alt_cal_c3gxb
# -- Compiling module alt_aeq_s4
# -- Compiling module alt_eyemon
# -- Compiling module alt_dfe
# -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller
# -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag
# -- Compiling module sld_signaltap
# -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader
# -- Compiling module altserial_flash_loader
# -- Compiling module altsource_probe
#
# Top level modules:
# lcell
# altpll
# altlvds_rx
# altlvds_tx
# dcfifo
# altaccumulate
# altmult_accum
# altmult_add
# altfp_mult
# altsqrt
# altclklock
# altddio_bidir
# altdpram
# alt3pram
# parallel_add
# scfifo
# altshift_taps
# a_graycounter
# altsquare
# altera_std_synchronizer_bundle
# alt_cal
# alt_cal_mm
# alt_cal_c3gxb
# alt_aeq_s4
# alt_eyemon
# alt_dfe
# sld_virtual_jtag
# sld_signaltap
# altstratixii_oct
# altparallel_flash_loader
# altserial_flash_loader
# altsource_probe
#
# vlib verilog_libs/altera_lnsim_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/altera_lnsim_ver".
# vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver
# Modifying modelsim.ini
# vlog -sv -work altera_lnsim_ver {d:/altera/10.1/quartus/eda/sim_lib/altera_lnsim.sv}
# Model Technology ModelSim SE vlog 6.6c Compiler 2010.08 Aug 23 2010
# -- Compiling module altera_pll
# -- Compiling package altera_lnsim_functions
# -- Compiling module generic_pll
# -- Importing package altera_lnsim_functions
# -- Compiling module generic_cdr
# -- Compiling module common_28nm_ram_pulse_generator
# -- Compiling module common_28nm_ram_register
# -- Compiling module common_28nm_ram_block
# -- Compiling module generic_m20k
# -- Compiling module common_28nm_mlab_cell_pulse_generator
# -- Compiling module common_28nm_mlab_cell
# -- Compiling module generic_mlab_cell
#
# Top level modules:
# altera_pll
# generic_cdr
# generic_m20k
# generic_mlab_cell
#
# vlib verilog_libs/cycloneii_ver
# ** Warning: (vlib-34) Library already exists at "verilog_libs/cycloneii_ver".
# vmap cycloneii_ver ./verilog_libs/cycloneii_ver
# Modifying modelsim.ini
# vlog -vlog01compat -work cycloneii_ver {d:/altera/10.1/quartus/eda/sim_lib/cycloneii_atoms.v}
# Model Technology ModelSim SE vlog 6.6c Compiler 2010.08 Aug 23 2010
# -- Compiling UDP CYCLONEII_PRIM_DFFE
# -- Compiling UDP CYCLONEII_PRIM_DFFEAS
# -- Compiling UDP CYCLONEII_PRIM_DFFEAS_HIGH
# -- Compiling module cycloneii_dffe
# -- Compiling module cycloneii_latch
# -- Compiling module cycloneii_mux21
# -- Compiling module cycloneii_mux41
# -- Compiling module cycloneii_and1
# -- Compiling module cycloneii_and16
# -- Compiling module cycloneii_bmux21
# -- Compiling module cycloneii_b17mux21
# -- Compiling module cycloneii_nmux21
# -- Compiling module cycloneii_b5mux21
# -- Compiling module cycloneii_ram_pulse_generator
# -- Compiling module cycloneii_ram_register
# -- Compiling module cycloneii_ram_block
# -- Compiling module cycloneii_jtag
# -- Compiling module cycloneii_crcblock
# -- Compiling module cycloneii_asmiblock
# -- Compiling module cycloneii_m_cntr
# -- Compiling module cycloneii_n_cntr
# -- Compiling module cycloneii_scale_cntr
# -- Compiling module cycloneii_pll_reg
# -- Compiling module cycloneii_pll
# -- Compiling module cycloneii_routing_wire
# -- Compiling module cycloneii_lcell_ff
# -- Compiling module cycloneii_lcell_comb
# -- Compiling module cycloneii_asynch_io
# -- Compiling module cycloneii_io
# -- Compiling module cycloneii_clk_delay_ctrl
# -- Compiling module cycloneii_clk_delay_cal_ctrl
# -- Compiling module cycloneii_ena_reg
# -- Compiling module cycloneii_clkctrl
# -- Compiling module cycloneii_mac_data_reg
# -- Compiling module cycloneii_mac_sign_reg
# -- Compiling module cycloneii_mac_mult_internal
# -- Compiling module cycloneii_mac_mult
# -- Compiling module cycloneii_mac_out
#
# Top level modules:
# cycloneii_latch
# cycloneii_and1
# cycloneii_and16
# cycloneii_bmux21
# cycloneii_b17mux21
# cycloneii_nmux21
# cycloneii_b5mux21
# cycloneii_ram_block
# cycloneii_jtag
# cycloneii_crcblock
# cycloneii_asmiblock
# cycloneii_pll
# cycloneii_routing_wire
# cycloneii_lcell_ff
# cycloneii_lcell_comb
# cycloneii_io
# cycloneii_clk_delay_ctrl
# cycloneii_clk_delay_cal_ctrl
# cycloneii_clkctrl
# cycloneii_mac_mult
# cycloneii_mac_out
#
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Modifying modelsim.ini
#
# vlog -vlog01compat -work work +incdir+F:/WORK_CODE/SRAM_Demo {F:/WORK_CODE/SRAM_Demo/ouravr.v}
# Model Technology ModelSim SE vlog 6.6c Compiler 2010.08 Aug 23 2010
# -- Compiling module ouravr
#
# Top level modules:
# ouravr
#
vsim -voptargs=+acc work.ouravr
# vsim -voptargs=+acc work.ouravr
# Loading work.ouravr
add wave \
{sim:/ouravr/clk } \
{sim:/ouravr/y1 } \
{sim:/ouravr/cnty1 }
force -freeze sim:/ouravr/clk 1 0, 0 {50 ns} -r 100
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run
run |
阿莫论坛20周年了!感谢大家的支持与爱护!!
该献的血还是要献的。你不献他不献。难道让我去献? --- 出自坛友:lovejp1981
|