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楼主 |
发表于 2010-10-13 16:24:10
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完整的程序像这样的,同步ain bin 的信号,产生一个脉冲,以改变计数器的值,最后用数码管显示
//由AB相产生脉冲并计数,显示
module decodeprj(ain,bin,rst,clk,dataout,en);
input ain,bin,rst,clk;
output[7:0] dataout;
output[7:0] en;//COM使能输出
reg[7:0] dataout;//各段数据输出
reg[7:0] en;
reg[31:0] cnt_scan;//扫描频率计数器
reg[3:0] dataout_buf;
// reg[32] bcdout;//16位计数器转化成的BCD码,4位一值
reg [2:0] RA_buf;
reg [2:0] RB_buf;
reg [2:0] FA_buf;
reg [2:0] FB_buf;
wire SysRA,SysFA,SysRB,SysFB;
trireg Ren,Fen;
reg[31:0] cnumberplus;
reg[31:0] cnumberminus;
reg[31:0] cnumber;//脉冲计数个数 16位空间 65536个数 um—mm级别
always@(negedge rst or posedge clk)
begin
if(!rst)
begin
RA_buf <= 0;
end
else RA_buf <= {RA_buf[1:0],ain};
end
assign SysRA = (RA_buf == 3'b011)? 1 : 0; //同步A的上升沿
always@(negedge rst or posedge clk)
begin
if(!rst)
begin
FA_buf <= 7;
end
else FA_buf <= {FA_buf[1:0],ain};
end
assign SysFA = (FA_buf == 3'b100)? 1 : 0; //同步A的下降沿
always@(negedge rst or posedge clk)
begin
if(!rst)
begin
RB_buf <= 0;
end
else RB_buf <= {RB_buf[1:0],ain};
end
assign SysRB = (RB_buf == 3'b011)? 1 : 0; //同步B的上升沿
always@(negedge rst or posedge clk)
begin
if(!rst)
begin
FB_buf <= 7;
end
else FB_buf <= {FB_buf[1:0],ain};
end
assign SysFB = (FB_buf == 3'b100)? 1 : 0; //同步B的下降沿
assign Ren = (SysRA & !bin) | (SysFA & bin) | (SysRB & ain) | (SysFB & !ain) ;
assign Fen = (SysRA & bin) | (SysFA & !bin) | (SysRB & !ain) | (SysFB & ain) ;
//use ain bin to TEST!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
always@(negedge rst or posedge Ren)
begin
if(!rst)
begin
cnumberplus <= 65536;
end
else
cnumberplus <= cnumberplus+1;
end
always@(negedge rst or posedge Fen)
begin
if(!rst)
begin
cnumberminus <= 0;
end
else
cnumberminus <= cnumberminus+1;
end
always@(cnumberminus or cnumberplus)
cnumber = cnumberplus - cnumberminus;
always@(posedge clk)
begin
cnt_scan<=cnt_scan+1;
end
always @(cnt_scan)
begin
case(cnt_scan[15:13])
3'b000 :
en = 8'b1111_1110;
3'b001 :
en = 8'b1111_1101;
3'b010 :
en = 8'b1111_1011;
3'b011 :
en = 8'b1111_0111;
3'b100 :
en = 8'b1110_1111;
3'b101 :
en = 8'b1101_1111;
3'b110 :
en = 8'b1011_1111;
3'b111 :
en = 8'b0111_1111;
default :
en = 8'b1111_1111;
endcase
end
always@(en or cnumber) //对应COM信号给出各段数据
begin
case(en)
8'b1111_1110:
dataout_buf<=cnumber[3:0];
8'b1111_1101:
dataout_buf<=cnumber[7:4];
8'b1111_1011:
dataout_buf<=cnumber[11:8];
8'b1111_0111:
dataout_buf<=cnumber[15:12];
8'b1110_1111:
dataout_buf<=cnumber[19:16];
8'b1101_1111:
dataout_buf<=cnumber[23:20];
8'b1011_1111:
dataout_buf<=cnumber[27:24];
8'b0111_1111:
dataout_buf<=cnumber[31:28];
default:
dataout_buf<=8;
endcase
end
always@(dataout_buf)
begin
case(dataout_buf)
4'b0000:
dataout=8'b0000_0011;
4'b0001:
dataout=8'b1001_1111;
4'b0010:
dataout=8'b0010_0101;
4'b0011:
dataout=8'b0000_1101;
4'b0100:
dataout=8'b1001_1001;
4'b0101:
dataout=8'b0100_1001;
4'b0110:
dataout=8'b0100_0001;
4'b0111:
dataout=8'b0001_1111;
4'b1000:
dataout=8'b0000_0001;
4'b1001:
dataout=8'b0001_1001;
4'b1010:
dataout=8'b0001_0001;
4'b1011:
dataout=8'b1100_0001;
4'b1100:
dataout=8'b0110_0011;
4'b1101:
dataout=8'b1000_0101;
4'b1110:
dataout=8'b0110_0001;
4'b1111:
dataout=8'b0111_0001;
default:
dataout=8'b1111_1111;
endcase
end
endmodule |
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