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module led(clck,led);
input clck;
output led;
reg [0:24] jinz;
reg [0:26] jinz2;
reg co,en,co1,en1,LED;
assign led=LED;
always @(posedge clck)
begin
if(en)
begin
if(jinz<20_000_000-1)begin jinz=jinz+1;co=0;end
else begin jinz=0;co=1;end
end
end
always @(posedge clck)
begin
if(en1)
begin
if(jinz2<80_000_000-1)begin jinz2=jinz2+1;co1=0;end
else begin jinz2=0;co1=1;end
end
end
always @(posedge co)
begin
en=0;
en1=1;
LED=1;
end
always @(posedge co1)
begin
en1=0;
en=1;
LED=0;
end
endmodule
assign led=LED;这条语句如果换成assign led=0;就没错了。为什么??? |
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该献的血还是要献的。你不献他不献。难道让我去献? --- 出自坛友:lovejp1981
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